Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
80
3.6.3 AC Timings
AGP3.0 timings are specified through two sets of parameters, one set that defines the AGP3.0 common
clock operation (for the outer loop control signals), and the second set that defines source synchronous
operation. Table 40 and Table 41 provide a summary of the interface timings for 66 MHz and 533 MT/s
AGP3.0 operation. The timings are divided between “common clock” for the arbitration signals and
“source synchronous” for data transmission and reception.
Table 40: AGP3.0 AC Timing Parameters, 66 MHz Common Clock
Symbol Parameter Min Max Units Notes / Comments
T
Skew
CLK Skew between
AGP3.0 devices
- 1.0 ns
T
CYC
CLK Cycle time 15 30 ns
T
HIGH
CLK high time 6.0 ns
T
LOW
CLK low time 6.0 ns
T
Val
CLK to command valid 1.0 5.5 ns Into std 50 Ω load to
Vss
T
Flt
Flight time to load - 2.5 ns Includes PCB traces and
connector(s)
T
SU
setup to CLK 6.0 ns
T
H
hold from CLK 0 ns
T
R
, T
F
Rise, Fall time 2.0 3.5 V/ns Measured into std 50 Ω
load to Vss