Accelerated Graphics Port Interface Specification
AGP3.0 Interface Specification
Rev. 1.0
99
Chipsets may guarantee any value for the maximum latency between zero and five isochronous periods
(L
max
= 5 microseconds). The specific value supported by the core-logic is indicated in a PCI
configuration register (NISTAT.isoch_L). Figure 4-1 shows how data transfers may occur in a system
where the core-logic latency is L
core-logic
= 2. The figure also illustrates the required transaction ordering
within a read or a write stream, and the lack of order between read and write streams.
Isochronous Parameters
N = 5
L = 2
R
1
W
1
R
2
W
2
Data
Request
No order between
read, write data
L
chipset
=2
AGP8X target could
t
ransfer data for R
1
here
AGP8X target must begin data
transfer for R
1
by here
R
1
W
1
W
2
R
2
Start of isochronous period
R
3
R
3
Figure 4-1: Isochronous Latency Determines Transfer Occurances
Figure 4-2 shows common values for the maximum number of transactions, latency and payload size
for various computer platform classes.
Platform Classes BW N L
max Y Usage
Perf WS 640 MB/s 5 10
128 2 HDTV streams
Entry WS 384 MB/s 3 10
128 1 HDTV stream
DT Enthusiast 320 MB/s 5 2
64 Video editing
DT Consumer 128 MB/s 2 2
64 Video capture
Platform Classes BW N
L
Y Usage
Perf WS 640 MB/s 5 10
128 2 HDTV streams
Entry WS 384 MB/s 3 10
128 1 HDTV stream
DT Enthusiast 320 MB/s 5 2
64 Video editing
DT Consumer 128 MB/s 2 2
64 Video capture
Figure 4-2: N, Y, and L Values Determine Platform Isochronous Class-level Service
Allowable choices of N, L and Y afford core-logic designers considerable freedom to adapt products to
the needs of their markets.
4.1.2.5 Isochronous Enqueueing Rules.
The following rules must be adhered to by the isochronous requester in order to guarantee the contract
latency. If violated the latency may exceed the chipset’s L value.
1. The request address must be naturally aligned on a Payload Size boundary. This prevents
memory thrashing, where each isochronous request requires multiple memory accesses
due to misalignment, which may result in read-modify-write operations in some memory
systems.
2. An isochronous stream may start on any payload size boundary, but must access
consecutive addresses until it reaches the end of an AGP page. This avoids frequent GART
TLB cache misses. However, a stream may end before reaching the end of an AGP page.