BIOS Settings Glossary version 13 - Alphabetical

BIOS Settings Dictionary – Alphabetical
V13 – November 2009
Hyper-Threading
Technology
This BIOS setting is
present only on Intel®
Desktop Boards that
support Hyper-
Threading Technology
if a processor
supporting Hyper-
Threading Technology
is installed.
Main • Disable
• Enable
Enables or disables Hyper-Threading Technology.
For information on Hyper-Threading, refer to
http://en.wikipedia.org/wiki/Hyperthreading
I
BIOS Setting Appears on
BIOS Screen…
Options Description / Purpose
ICH Temperature Advanced >
Hardware
Monitoring
No changeable
options
Displays temperature in the ICH zone.
Refer to the board's Technical Product Specification for the exact
location of this sensor.
IDE Auto-Detection Advanced >
Drive
Configuration
No changeable
options
Pressing Enter auto-detects the specs of the drive (size, cylinders,
heads, etc.)
Idle Time Out Intel® ME >
Intel®
Management
Engine
Configuration
User defined
A value between 0 and 65535. Sets the number of minutes of idle
time before Intel® ME will sleep.
Default value is 0. With this setting, Intel® ME will not sleep, with
no power savings.
This option is present only if “Turn on Intel® ME in Sleep States” is
enabled.
IGD Aperture Size Advanced >
Video
Configuration
• 4MB
• 8MB
• 16MB
• 32MB
• 128MB
• 256MB
Options may
vary depending
on board model.
Establishes the maximum amount of system memory that the
Operating System can use for video memory. This is primarily
used for buffering textures for the AGP video device.
IGD DVMT
Memory
Advanced >
Video
Configuration
• 32MB
• 64 MB
• 128 MB
• Maximum
DVMT
Intel Dynamic Video Memory Technology 3.0 (DVMT 3.0) allows
additional memory to be allocated for graphics usage based on
application need. Once the application is closed, the memory that
was allocated for graphics usage is then released and made
available for system use.
Maximum DVMT allows up to 224 MB of memory to be allocated
for graphics.
For information on DVMT, refer to the Intel® Graphics Media
Accelerator 900 White Paper at
http://www.intel.com/design/chipsets/applnots/30262403.pdf