Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
101
data, then write an isochronous synchronization flag in system memory using a fenced write
transaction. Once the flag becomes visible, the data is guaranteed to be visible. Isochronous data may
be written with fenced or unfenced write transactions; however, completion flags must be written with a
fenced write transaction.
Synchronizing the processor with an AGP3.0 Isoch. Write could proceed as follows:
AGP3.0 device writes data (unfenced isoch write transaction)
AGP3.0 device writes flag (fenced isoch write transaction)
AGP3.0 signals processor
Processor enters polling loop in response to signal
Processor breaks out of polling loop when flag comes true
Processor consumes data
Signaling the processor could be done via interrupts, or done implicitly by means of a periodic task
scheduling service in the operating system. Since both signaling methods are unordered with respect
to the arrival of data, the polling loop prevents premature processing of the data.
4.1.4 Guaranteed Global Visibility
An AGP3.0 core-logic must make isochronous write data globally visible to the system without the need
for an explicit flush operation. This ensures that write data cannot remain invisible inside the core-logic
for an indefinite amount of time.
4.1.5 Coherent Isochronous Requests
An isochronous request must not target coherent AGP3.0 address space. Coherent address space is
defined as any region in the AGP3.0 address space where the core-logic enforces cache coherency in
hardware. Any isochronous request into such a space will result in a platform specific exception
condition. The method of disposition of such a request is also platform specific.
4.1.5.1 Memory Attributes for Isochronous Requests
Within the AGP3.0 aperture (see sec 5.3) the following memory types are supported:
1. Write-Combining/Non-Coherent: Processor accesses into this region are treated as
uncached, non-coherent and “write-combining”. AGP3.0 accesses are also treated as non-
coherent with no hardware enforced coherency checks. Isochronous requests are allowed in
this region.
2. Write-Back/Coherent: Processor accesses to this region are considered cache-coherent and
core-logic will perform hardware enforced coherency checks for AGP3.0 accesses. Isochronous
requests are disallowed in this region.
3. Write-Back/Non-Coherent: In this region processor accesses are cache coherent (write-back
space) while AGP3.0 accesses are treated as non-coherent with no hardware coherency
checks. Isochronous requests are allowed in this region.
Note that isochronous accesses are not permitted outside the AGP3.0 aperture since such accesses
are always treated as coherent by the core-logic