Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
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Master is allowed to disconnect a stalled transaction with or without accepting any data. The target is
required to resume where the disconnected transaction left off.
Disconnecting a stalled Fast Write ensures that a pending isochronous transfer can complete in a
timely manner.
4.3 Synchronization Models
This section presents a discussion of the synchronization models used for interchange of data between
different agents in the platform. The basic reason for synchronization is to guarantee that when one
agent performs a data movement in the platform for consumption by a second agent, the second agent
receives the intended data.
There are several instances of this as presented in the following list:
1. Processor writes data to Main Memory and AGP3.0 device reads this data.
2. AGP3.0 device writes data to Main Memory and the processor reads this data.
3. A 3
rd
agent (say another PCI device) writes to Main Memory and AGP3.0 device reads this data.
4. AGP3.0 device writes to the Main Memory and a 3
rd
agent reads this data.
5. One AGP3.0 device behind a Fan-out Bridge writes to the Main Memory, while the other AGP3.0
devices behind the same bridge read it.
/ NOTE
The mechanisms that apply to sections 1 and 2 above generally work for the rest. However, the
method used to signal the other agent varies.
A few terms need to be defined before we proceed to synchronization schemes.
4.3.1 Global Visibility
A write to system memory reaches global visibility when all agents accessing that memory address get
the updated data. As an example, consider an AGP write to system memory location A. If the write data
is sitting in a write buffer within the AGP Port and the core-logic does not consider this write buffer as
part of the globally visible state, a subsequent access to location A does not read the contents of this
buffer. The “write data” then has not reached a state of global visibility. If the write data moves into a
posted write buffer in the memory controller that is checked on every subsequent access from
anywhere in the system, then the write data is now globally visible and no other (or older copies) of this
data matters. Another way to define the point of global visibility is as a point of serialization of all
requests from anywhere in the system. If the state being modified is in cacheable space, the global
visibility is attained only after the cache coherency enforcement has been completed.
4.3.2 Request Completion
• A Write request is completed only after the state being modified is globally visible.
• A Read request has two levels of completion:
1. When the data fetch has taken place implying that the data to be returned is now committed.
2. The actual return of data to the requesting agent.