Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
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Since the second phase is eventually completed, the completion of the first phase (which decides on
the data to be returned) is more important.
4.3.3 Write Completion
Since “Writes” from any agent (processor, or AGP3.0 for example) device may be posted, this data
could potentially sit in write queues indefinitely. This is especially true if there are dependencies on
subsequent events (such as more writes) to flush these queues.
The AGP3.0 specification then requires that all AGP3.0 initiated writes to system memory must be
completed in a timely fashion, without the need for any other system event. While no actual time is
being specified for this completion, it is expected that the core-logic shall ensure that these writes have
a fair and timely opportunity to propagate to the point of global visibility.
This process applies to both asynchronous and isochronous writes. The guaranteed write completion
ensures that a FLUSH is not required on the AGP3.0 interface forcing a write to completion.
4.3.4 Synchronization Case 1: Processor Data to AGP
The following scheme ensures correct operation.
Table 52: The Synchronization Sequence of Data from Processor to AGP
Processor Actions Core-logic Actions AGP Device Actions
Writes (or flushes cache) data to
System Memory (either WC or WB
Space).
Accumulates writes in posted write
buffers. Performs any Coherency
operations.
Polls for flag indicating buffer availability to set
Executes un-cached access such
as an I/O space read or write.
Flushes all posted write buffers into
system memory (or to global visibility)
before completing un-cached
transaction.
Polls for flag to set
25
Signals to AGP3.0 Device by
reading or writing I/O register or
writing memory location to set flag
Guarantees that this write (to AGP
Device or memory) will complete after
write buffers are flushed.
Finds flag set and begins to read the data that
processor wrote in memory.
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This signal to a AGP3.0 Device may be merged with Step 2 that causes core-logic to flush buffers.