Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
113
5 Appendix B: Workstation Programming
Model
5.1 System Components
AGP8X
(Secondary PCI) Bus
AGP8X PORT
P2P Bridge
C F G
AGP8X Target
AGP8X
Device 1
AGP8X
Master
C F G
AGP8X
Device 2
AGP8X
Master
C F G
AGP8X (Secondary PCI) Bus
AGP8X PORT
P2P Bridge
C F G
AGP8X Target
AGP8X
Device 1
AGP8X
Master
C F G
AGP8X
Device 2
AGP8X
Master
C F G
Logical Primary PCI Bus
HOST
Bridge
C F G
Logical Host Bus
HOST
Processor(s)
MEMORY
PCI PORT
P2P Bridge
C F G
Graphics
Aperture
GART
Graphics
Aperture
GART
Figure 5-1: AGP3.0 Generalized Logical System Overview
Figure 5-1 illustrates a typical host Bus bridge (also known as core-logic) implementation that supports
the AGP interface along with other typical interfaces (or ports). Ports, other than the AGP3.0 Port, of the
core-logic are included for illustrative purposes only and are not required by this interface specification.
The example core-logic provides ports to the processor, system memory, the PCI Bus, and to AGP3.0.