Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
114
5.2 Port and Device Definitions
1. AGP3.0 Port: The AGP3.0 Port is the target of requests from the AGP3.0 (Master) devices. It is
provided by the core-logic implementation. AGP3.0 provides for multiple AGP3.0 Ports with multiple
devices on each port.
2. Processor Port: The processor port is not required when supporting an AGP3.0 interface, but is
typically supported by a Host Bus Bridge. The processor port provides a means for the processor to
generate accesses to the PCI Ports, AGP3.0 Port, and to the memory controller. The core-logic
determines to which port these accesses are routed by using information stored in the Host Bus
Bridge Configuration Space block. This information is provided during the initialization process.
3. PCI Port: The PCI Port converts processor accesses into PCI transactions. Since the processor
has no Configuration commands, the PCI Port generates PCI Configuration commands as
described in the PCI Local Bus Specification. The PCI Port takes memory commands that address
system memory and forwards them to the Memory controller. The AGP3.0 specification only
requires the PCI Port controller to provide a means for PCI masters to have peer-to-peer write
access to the PCI target that resides on the AGP3.0 Port.
4. MEM Port: This port provides a means to connect system memory to the core-logic. The memory
controller is responsible for converting accesses that are initiated on other ports (processor,
AGP3.0, and PCI) into memory commands.
When the core-logic supports an AGP3.0 Port, it requires new logic that has not been incorporated in
previous core-logics, however no new functionality is required to boot the system. To enable the use of
existing enumeration code to handle AGP3.0 devices, the core-logic will use functionality already defined
by the PCI Local Bus Specification. The Configuration Space of the Bridge containing the AGP3.0 Port
also contains configuration registers used to specify parameters associated with the GART and circuitry
in the AGP3.0 interface.
5.2.1 AGP Master Device Memory Reference
AGP Master devices have a certain amount of memory resources that must be placed somewhere in
the system memory address map using a PCI base address register. These memory resources fall
into two categories, prefetchable and non-prefetchable, address regions. Prefetchable memory space
is generally where the linear frame buffer is mapped to provide performance improvements. Non-
prefetchable memory space is generally where control registers and FIFO-like communication
interfaces are mapped. Each of these address regions should have its own base address register.
See the PCI Local Bus Specification for a description of PCI base address registers.