Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
115
5.2.2 AGP3.0 Port Requirements
1. The core-logic locates all AGP3.0 configuration registers within a single function of the AGP3.0 Port
device; this allows System Software to easily support AGP3.0. The core-logic ensures that the
configuration of all AGP3.0 Port resources, AGP3.0 aperture, and GART reside within this single
function space. The registers are described in more detail later in this section.
2. The location of AGP3.0 configuration registers may either be in the core-logic’s Host Bridge or all
within a PCI-to-PCI bridge or both.
3. It may be possible for a core-logic implementation to place AGP3.0 configuration registers in a Host-
Bridge device; it is not known at this time if this will work across various future operating systems or
allow a portable software device driver. However, such hardware implementations may be
unavoidable and so the AGP3.0 specification allows it.
4. Core-logic provides each AGP3.0 Port with a separate, independent Graphics AGP3.0 aperture and
GART that is shared by all devices on that port.
5. Each AGP3.0 device on a given AGP3.0 Port resides on the bridge’s PCI side; each AGP3.0 device
has a unique PCI Device address on this interconnect.
AGP3.0 does not, in general, require the support of PCI Peer-to-Peer accesses. Devices needing to
share data do it through shared buffers in system memory. Note that the AGP3.0 specification explicitly
relaxes some peer-to-peer requirements of the PCI-to-PCI Bridge Specification. See the following
below. Table 54 describes the requirements. In this table, “AGP3.0
a
” represents one AGP3.0 port in the
platform. A “non-AGP3.0
a
” port could be another PCI or a different I/O port. The “type” field represents
the transaction on the initiator’s port.
Table 54: PCI Peer-to-Peer Access
Initiated From Targeted To Type Support
Device(Port == AGP3.0a) Device(Port != AGP3.0a) AGP3.0 / PCI Read and Write Not
Required
Device(Port == AGP3.0a) Device(Port == AGP3.0a) AGP3.0 / PCI Read and Write Not
Required
Device(Port != AGP3.0a) Device(Port == AGP3.0a) AGP3.0 or PCI Read Not
Required
Device(Port != AGP3.0a) Device(Port == AGP3.0a) AGP3.0 Fast Write or PCI
Write
Required
5.2.3 Multiple AGP3.0 Ports
AGP3.0 allows a core-logic implementation to provide multiple AGP3.0 Ports. Each AGP3.0 Port is a
bridge device with multiple AGP3.0 devices hanging off the secondary bus. Each Port has a separate
Graphics AGP aperture and GART that is independent and not shared with another AGP3.0 Port;
however, these are shared across the devices within a single AGP3.0 Port.