Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
117
An AGP3.0 target (core-logic) may implement a number of Graphics Translation Look-aside Buffers
(GTLB) to speed-up translation of AGP3.0 aperture page addresses to system memory locations.
5.3.1 AGP Aperture Page Size
The core-logic implementation is configured by system software to support one, common AGP aperture
page size for all pages in the AGP aperture. The core-logic includes a mechanism that allows system
software to select that common AGP3.0 aperture page size from a set of supported page sizes. At any
given time, one and only one AGP3.0 aperture page size is used for all pages within the AGP aperture.
Core-logic indicates which AGP aperture page sizes are supported through the NEPG register. System
software selects one page size from the set of supported AGP aperture page sizes by programming the
value into the NEPG.SEL. A core logic implementation must always support an AGP aperture page size
of 4 KB; implementations are encouraged, but not required to support other AGP aperture page sizes.
(Note that NEPG defaults to selecting 4-KB AGP aperture pages.)
System software populates (maps) each AGP aperture page with a same-sized, naturally aligned region
from physical memory. Note that there need be no correspondence between the host processor page
size and the AGP aperture page size used by core logic. The only requirement is that each populated
AGP aperture page translates to a fully allocated and resident physical memory region that is of equal
size and is naturally aligned.
When given the choice, System Software should select the largest AGP aperture Page size that is
compatible with operating system memory allocation algorithms. Larger AGP aperture page sizes
reduce the size of the GART; allow more freedom in which system pages can be mapped into the AGP
aperture; and can allow an implementation to improve the efficiency of GART translations.
5.3.2 AGP Graphics Aperture Requirements
1. To configure the size of the AGP aperture, use the software programmable APSIZE to select the
desired AGPaperture size. The selected AGP aperture size causes the low-order bits of APBASE to
be read-as-zero, thus forcing natural alignment of the AGP aperture.
2. Software sizes and locates the AGPaperture by programming the APBASE base registers
(APBASELO and APBASEHI). Core-logic implementations that only support 32-bit physical
addressing do not need to implement APBASEHI.
3. AGPCTRL.aperenb enables translations through the AGP aperture of AGP Master Accesses. When
the AGP aperture is disabled, AGP3.0 Master accesses to the AGP aperture range are treated by
the Core-logic exactly in the same manner as AGP3.0 Master accesses outside of the AGP
aperture.
4. System software (and the BIOS) must ensure that the AGP aperture is located within the address
range that can be addressed by the AGP device. This range can be determined by checking
AGPSTAT.OVER4G and AGPCMD.OVER4G of both AGP Master and Target.
5. Core-logic implementations are strongly encouraged to support a range of AGP aperture sizes that
span 16MB-256MB. Larger aperture sizes of 1GB or more would be appropriate for higher end
workstation platforms.
6. All AGP Master accesses that fall within the AGP aperture are translated regardless of protocol
when the AGP aperture is enabled; this is termed AGP Master translation.
7. The Core-logic must support AGP Master access to locations outside of the AGP aperture.
8. The Core-logic is not required by the AGP specification to translate accesses directed to the AGP
aperture by a host processor – termed host translation. Portable AGP3.0 software should not rely
upon the existence of host translation.
9. If core-logic supports host translation, it reports the capability in AGPSTAT.htrans#. Host-translation