Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
121
5.4 Coherency Requirements
When the AGP target makes an access from an AGP Master coherent, the target ensures that:
• A read request receives the most current value of the datum from among all host processor
caches, memory, and other coherent caching agents in the system;
• A write request’s value becomes the most current value of the datum in the system and is made
visible to all host processor caches, memory, and other coherent caching agents in the system.
When the AGP target does not make an access from an AGP Master coherent, the target need only
update system memory without affecting the state of any caching agent in the system.
When the AGP target is not required to provide a specific coherency for an access, it is unpredictable if
the above coherency guarantees are provided for the access; whether coherency is provided can
change from moment to moment and implementation to implementation. When no specific coherency
is required for an access, software should not rely upon coherency being provided.
Coherency is applied by the AGP Target to addresses generated after GART translations, rather than to
the actual Graphics AGP aperture addresses, for access within the Graphics AGP aperture.
Table 56 identifies the actions of the AGP target that apply to any type of protocol access (AGP or PCI)
made by an AGP Master:
Table 56: Coherency Table
Inside Graphics
AGP Aperture
Protocol-Type AGPSTAT.ita_coh
(Support for Coherency
inside AGP3.0 aperture?)
Gart_entry.coh Coherency Action
Ensured by AGP Target
NO X X X Access is coherent
YES X 1 1 Access is coherent
YES X 0 1 Specific coherency not
required for Access
YES Not PCI-Protocol X 0 Access is not coherent
YES PCI-Protocol X 0 Specific coherency not
required for Access
It is implementation-dependent and outside the scope of the AGP3.0 specification whether a core-logic
implementation supports coherency for accesses to the graphics AGP aperture from masters not on
the AGP Port.