Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
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5.4.1 Coherency of Host Processor Accesses
The coherency mechanisms described in the AGP3.0 specification do not control nor influence the
coherency of any host processor access to any region of physical memory, including the Graphics AGP
aperture. Thus, the coherency of a host processor access to a graphics AGP aperture page would
ignore the value of the page’s gart_entry.coh bit, and all other such mechanisms described above.
When the AGP Target supports host translation through the AGP aperture (AGPSTAT.htrans# is ‘0’), it
is recommended that software not use GART entries with gart_entry.coh set to ‘1’. This mode of
operation can result in unpredictable coherency for accesses. The unpredictable nature is because host
processor accesses will have coherency applied to the pre-GART address using processor coherency
controls. However, AGP Master accesses will have coherency applied to the post-GART address using
gart_entry.coh. Table 57 describes the coherency behavior of the core-logic based on whether host
processor accesses are translated or not. All accesses are assumed to target the AGP aperture.
Table 57: Host translation effect on Core-Logic behavior
5.5 System Software Initialization
The operating system initializes AGP3.0 features by performing the following operations:
1. Allocate memory for the AGP remapping table.
2. Initialize the AGP target’s address remapping hardware.
3. Set the AGP target and master data transfer parameters.
4. Set host memory type for AGP memory.
5. Activate policy limiting the amount of AGP memory.
An AGP core-logic driver API will be used for the second item. Refer to the appropriate Operating
System device driver interface kit for details.
The third item requires access to configuration registers defined later in this interface specification.
Reading bit 4 set to 1 in the Status register at offset 6 indicates the device implements the New
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Core-logic must ensure that any buffers with post-GART addresses are also included in the coherency check.
Htrans# ita_coh gart_entry_coh Target response to AGP Access
0 0 X Non-Coherent access
0 1 0 Non-Coherent access
0 1 1 Coherent access. Core-logic
uses Pre-GART address for
coherency check.
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This mode of
operation is not recommended.
1 0 X Non-Coherent access
1 1 0 Non-Coherent access
1 1 1 Coherent access. Core-Logic
uses Post-GART address for
coherency check.