Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
124
These registers are located in AGP configuration space of the core-logic (also called AGP target) and
AGP Device (also called AGP Master). For the core-logic, the AGP configuration space could be entirely
in a Host-to-PCI Bridge function and/or a PCI-to-PCI Bridge function.
NOTES
:
=
Register is in target (core-logic) only. Use of these
in the master (graphics chip) is undefined
.
= Register is in both target and master
: + 20h
CAPPTR
: + 00h
: + 04h
: + 14h
: + 10h
: + 0Ch
: + 08h
: + 18h
: + 1Ch
: 10h
: 14h
: 34h
: + 24h
: + 28h
byte 0 byte 1 byte 2 byte 3
apsize
: + 2Ch
apbasehi
(optional )
garthi
(optional )
NCAPID
AGPSTAT
AGPCMD
AGPctrl
gartlo
apbaselo
reserved
reserved
reserved
NISTAT
(optional )
AGP Capability Block
NICMD
(optional )
nepg
(optional )
Figure 5-4: AGP3.0 Configuration Register Space
5.6.1 Register Set Support Requirements
A Target or Master may choose to implement just the Core Specification Register set or the enhanced
superset described in the Appendix. Even when implementing the superset, the implementation
needs to only consider the registers that support the core and optional features being included
in the design. Note that the Core Register Set described in Chapter 2 is a superset of the current
AGP2.0 Register Set and is backward compatible from a legacy software perspective. The enhanced
register set described here is a superset of both the AGP Core and the AGP2.0 register set. However,
compatibility with legacy software environments cannot necessarily be assumed as GART and AGP
aperture programming implementations have varied in the past. Furthermore, enabling of any new
features described in the Appendices will require new software.