Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
128
5.8.4 AGPSTAT: AGP STATUS REGISTER
Offset:
CAPPTR + 04h
Size: 4 bytes
Table 64: Status Register
Bits Access Field Description
31:24 MST: R1-IW
TGT: R-IW-Dx
RQ TARGET ONLY: The RQ field contains the maximum number of AGP3.0
command requests (both asynchronous and isochronous) that can be
enqueued to the target. “0” means a depth of 1 entry, while 0xFF means
a depth of 256 entries.
23:18 RZ-IW Reserved Always returns 0 when read; write operations have no effect.
17 R-IW-Dx ISOCH
SUPPORT
TARGET & MASTER:
‘0’ = Isoch transactions not supported
‘1’ = Isoch transactions supported
Note:
1. If ‘0’, optional NISTAT and NICMD registers are not implemented
and should be ignored by software.
2. Isoch is not supported when 4x speed operation is selected.
When this happens this bit will be forced by hardware to 0
16 RZ-IW Reserved Always returns 0 when read; write operations have no effect.
15:13 MST: RZ-IW
TGT: R-IW-Dx
ARQSZ TARGET ONLY: LOG2 of the optimum asynchronous request size in
bytes minus 4 to be used with the target. The MASTER should attempt to
issue a group of sequential back-to-back asynchronous requests that
total to this size and for which the group is naturally aligned to.
Optimum_request_size = 2 ^ (ARQSZ+4)
If ARQSZ is zero, then the target has no recommendation.
12:10 R-IW-Dx CAL_Cycle MASTER & TARGET: Specifies required period for core-logic
initiated bus cycle for calibrating I/O buffers.
CAL_CYCLE Period
000 4 ms
001 16ms
010 64 ms
011 256 ms
100-110 Reserved for future use
111 Calibration Cycle Not Needed
9 R1-IW Reserved (SBA) Always returns 1 when read; write operations have no effect.
AGP3.0 devices are required to support side band addressing,
even when operating in AGP 2.0 compatibility mode.
8 MST: RZ-IW
TGT: R-IW-Dx
ITA_COH TARGET ONLY: When ‘1’, the AGP3.0 target ensures that accesses from
an AGP Master are made coherent with host processor caches and other
caching agents in the system if the following are met:
Access is Inside The AGP aperture (ITA)
Access has corresponding gart_entry.coh bit set
7 MST: RZ-IW
TGT: R-IW-Dx
GART64B TARGET ONLY: When ‘1’, Core-logic can support 64-bit and 32-bit GART
entries; when ‘0’, only 32-bit GART entries are supported.