Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
139
5.9.3 AGPCTRL: AGP CONTROL REGISTER
Offset: CAPPTR + 10h
Size: 4 bytes
Table 70: Control Register
Bits Access Field Description
31:24 RZ-MW Reserved Reserved For Future AGP3.0 Architectural Core-logic
Features
23:16 R-MW-Dx Reserved Reserved For Implementation-Specific Core-logic Features
15:10 RZ-MW Reserved Reserved For Future AGP3.0 Architectural Core-logic
Features
9 R-W-D’0 CAL_CYCLE_DIS When set to ‘1’, calibration cycle operation is disabled by the
core-logic. Note that calibration cycle should be automatically
disabled by core-logic when not in AGP3.0 mode of operation
(see AGPSTAT[3])
8 R-W-D’0 APERENB
This bit controls the enabling of the graphics AGP aperture for
the AGP3.0 Port. When this bit is ‘1’, the AGP aperture is
enabled; when ‘0’ the AGP aperture is disabled.
7 R-W-D’0 GTLBEN
33 GTLB Enable (GTLBEN) -
This bit is available only if the core-logic implements a
Graphics Translation Look-aside Buffer (GTLB). If no GTLB
is implemented this bit is hardwired to ‘0’.
When set to 1 this bit enables normal operations of the
Graphics Translation Lookaside Buffer. If it is zero (default)
the GTLB is flushed by clearing the valid bits associated with
each entry. In this mode of operation all accesses that require
translation bypass the GTLB. All requests that are positively
decoded to the graphics AGP aperture force the Core-logic to
access the translation table in main memory before
completing the request. Translation table entry fetches will
not be cached in the GTLB.
6:0 R-MW-Dx Reserved Reserved For Implementation-Specific Core-logic Features