Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
14
1.5.1 Changes to AGP
The tables that follow describe the changes to AGP2.0. Descriptions of these changes are in the
chapters and appendices that follow.
Table 3: Changes to AGP2.0 in Core Specs
Change Section Classification Core-logic Impact Graphics Card Impact
8X (533MT/s) transfer rate
for Data and Side-band
Address (SBA)
2.1.2 Performance Required Required
Parallel terminated, low
voltage signaling
2.1 Performance Required Required
Hardware enforced
coherency outside GART
range for all transactions
2.4.1 Feature change Required Optional
“Long” Transaction Types
Removed
2.3.2 Feature Removal Required Required
No PIPE mode Addresses 2.3.1 Feature Removal Need not support PIPE Required
High Priority Transaction
Support Removed
2.3.2 Feature Removal Required Cannot use HP
transactions
Some changes to ordering
rules
2.3.4 Performance Optional Required
3.3 V AGP signaling. 2.4.2 Feature Removal
1.5V AGP signaling still
supported in “Universal
Mode”
Need not support
3.3V AGP
Supported in a Universal
AGP3.0 implementation
Calibration Cycle 2.1.3 Performance Required Required
Core-logic AGP Resources
in PCI-to-PCI Bridge
2.5 Feature Enhancement Optional No Impact
Dynamic Bus Inversion 2.1.3.b Performance Required Required