Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
140
5.9.4 APSIZE: AGP APERTURE SIZE
Offset: CAPPTR + 14h
Size: 2 bytes
Table 71: Aperture
Bits Access Field Description
15:12 RZ-MW Reserved Reserved
11:0 R-W-
D’111100
000000
APSIZE APSIZE[11:0] determines the status of APBASE[31:22] as
follows:
APSIZE[n] = 0 forces APBASE[22+n] to 0 when 0<=n=<5
APSIZE[n] = 0 forces APBASE[22+(n-2)] to 0 when 8<=n=<11
APSIZE[n] = 1 allows APBASE[22+n] is R/W programmable
when 0<n<5
APSIZE[n] = 1 allows APBASE[22+(n-2)] is R/W
programmable when 8<=n=<11
For legacy compatibility, APSIZE[7:6] should always be 00
and are not used.
APSIZE[11:0] have the following legal codes:
Bits: 11 10 9 8 7 6 5 4 3 2 1 0 Aperture Size
1 1 1 1 0 0 1 1 1 1 1 1 4MB
1 1 1 1 0 0 1 1 1 1 1 0 8MB
1 1 1 1 0 0 1 1 1 1 0 0 16MB
1 1 1 1 0 0 1 1 1 0 0 0 32MB
1 1 1 1 0 0 1 1 0 0 0 0 64MB
1 1 1 1 0 0 1 0 0 0 0 0 128MB
1 1 1 1 0 0 0 0 0 0 0 0 256MB Default
1 1 1 0 0 0 0 0 0 0 0 0 512MB
1 1 0 0 0 0 0 0 0 0 0 0 1024MB
1 0 0 0 0 0 0 0 0 0 0 0 2048MB
0 0 0 0 0 0 0 0 0 0 0 0 4096MB
A given core logic implementation may have a partial range of
aperture sizes from the above table. The following rules
apply:
• There must be a single contiguous range of
aperture sizes from the table above. –i.e. no gaps.
• Max Aperture Size: If this is different from the max in
the above table, the core logic must hardwire the