Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
143
6 Appendix C: Glossary of Terms
Term Definition
Common Clock Transfer A transfer across an interface between two agents that is synchronized to a clock that is
common to both and is matched in phase and frequency.
Core-logic The core-logic that has the host platform’s AGP3.0 bridge.
Motherboard This is a general term referring to the PC board that includes the components of the Core-
logic and the AGP connector.
MT/s Million Transfers/second where the size of the transfer is determined by the width of the
interface. So, in AGP3.0 the data bus does a maximum of (8x)533 MT/s, which on a 4-byte
interface translates to 2 Gbytes/s.
AGP3.0 Card, Graphics
Card
These refer to the Graphics Card that is installed into the AGP3.0 Connector.
AGP3.0 Master, AGP3.0
Device
The graphics chip that initiates AGP transactions.
AGP3.0 Mode The mode in which the AGP3.0 signaling and features are enabled.
AGP3.0 Target The core-logic during any AGP transaction. The graphics chip can also function as target
during core-logic initiated PCI transactions.
AGP3.0 Transactions Transactions on the AGP Interface using the AGP protocol semantics initiated by the AGP
Master using the Side-Band Address Interface. The core-logic initiated Fast-Write
transaction also falls under the category of AGP Transaction.
DBI Dynamic Bus Inversion. Scheme using dynamic inverting of data bits based on transition
history in order to limit the maximum number of simultaneous transitions.
PCI Transactions Any transaction on either the AGP or PCI interfaces that use the PCI protocol semantics.
Source Synchronous
Transfer
A transfer across an interface between two agents where the sender transmits a strobe
along with the data to capture and hold the data at the receiver.
Universal AGP3.0 Card A graphics card that supports both AGP3.0 and AGP1.5 V signaling and protocols.
Universal AGP3.0
Motherboard
A motherboard that supports both AGP3.0 and AGP1.5 V signaling and protocols.
Block-Level Flow Control This is used by the AGP Master to control the flow of data to or from the AGP target during
the actual data transfer phase. The mechanism used is suppression of TRDY during
cycles known as “throttle points” in the data phase. For a description of throttle points refer
to the AGP2.0 interface specification.
Buffer-Full Flow Control This is used by the AGP Master or Target (in the case of Fast Writes) to stall the start of
new data transfer transaction. The signals used for this purpose are RBF and WBF. For a
detailed description of using RBF and WBF refer to the AGP2.0 interface specification.