Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
3
Revision History
Revision # Date Description
V0.9 Nov. 2000 First public release of the draft specification
V0.91 Dec. 2000 Several corrections made after initial review. Major items
listed below:
• FW made optional for both target and master –
Sections: 2.7.4, 2.7.5, 5.8.4, 5.8.5
• SBA requests may start on any SB_STBx edge –
Section: 2.1.2
• Clarification on “sticky” Type requests on SBA –
Section: 2.3.2c
• Tval changed to 5.5ns – Tables: 21 & 29
• Outbound DAC transaction support from core-logic
made optional. – Sections: 2.7.4, 5.8.4
• Several editorial corrections made throughout
specification
V0.91R Apr. 2001 Table 7 corrected to make AGP Fast Writes optional for
Core Logic
V0.95 May 2001 Major changes include:
• Calibration Cycle transaction protocol changed.
• DBI made mandatory for AGP Transmitter
• DBI pin assignment on AGP connector changed
• CAP ID changes for AGP Target
• Updates to AC and DC timing specifications
• 64b AGP8X section removed from Appendix A
• Several minor inaccuracies corrected throughout
document
• Editorial corrections throughout document.
• 4X speed operation in AGP3.0 signaling mode
added
• AGP3.0 introduced as the new name for the AGP8X
Interface Specification
V1.0 August 2002 Major Changes include:
• SBA Clarification on Figure 5, ECN #3-01
• AGP3.0 timing specs for 4x speed, ECN #3-04
• Isochronous Rules, ECN #3-09
• PISOCH_Y and PISOCH_N, ECN #3-14
• Minimum Slew Rate Spec, ECN #3-17
• Apbase Clarification, ECN #3-18
• GART Width Clarification, ECN #3-20
• 3.3V Support, ECN #3-21
• 3.3V Standby Current Requirements, ECN #3-24
• Vddq Voltage Dependence, ECN #3-25
• Interconnect Layout Clarifications, ECN #3-26
• Overshoot and Ringback, ECN #3-27
• Local Vref Generation, ECN #3-28
• Calibration and Strobe Glitch, ECN #3-34