Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification

Rev. 1.0

2.5 AGP3.0 Programming

The configuration of registers in the AGP port, for the core-logic and graphics card is described below.

This has not changed from AGP2.0. However, there are changes to some of the fields in the NCAPID,

AGPSTAT and AGPCMD registers. These are described in this section. Additional changes to support

certain workstation specific optional features are described in Appendix B.

AGP requires all core-logic AGP configuration registers to be entirely located in a Host-to-PCI Bridge.

AGP3.0 eases this restriction by allowing all of the core-logic AGP3.0 configuration registers to be

entirely located in a Host-to-PCI and/or a PCI-to-PCI Bridge function. Splitting the register set across

the two bridge types is not allowed.

Figure 2-10: AGP3.0 Configuration Register Space

Status

AGP Status Register

AGP Command Register

ID=02h

34h

04h

Command

Minor

Major

Capability Registers

(

last device)

NULL

Capability Pointer

Bit 4

Optional AGP Register (See Appendix B)

PCI Status Register

AGP3.0 ID

Optional AGP Register (See Appendix B)