Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
47
2.7.4 AGPSTAT: AGP STATUS REGISTER
Offset: CAPPTR + 04h
Size: 4 bytes
Table 27: AGP Register
Bits Access Field Description
31:24 MST: R1-IW
TGT: R-IW-Dx
RQ TARGET ONLY: The RQ field contains the maximum number
of AGP command requests that can be enqueued to the
target. “0” means a depth of 1 entry, while 0xFF means a
depth of 256 entries.
23:16 RZ-IW Reserved Always returns 0 when read; write operations have no effect.
15:13 MST: RZ-IW
TGT: R-IW-D’x
ARQSZ TARGET ONLY: LOG2 of the optimum asynchronous request
size in bytes minus 4 to be used with the target. The MASTER
should attempt to issue a group of sequential back-to-back
asynchronous requests that total to this size and for which the
group is naturally aligned.
Optimum_request_size = 2 ^ (ARQSZ+4)
If ARQSZ is zero, then the target has no recommendation.
12:10 R-IW-Dx CAL_Cycle MASTER & TARGET: Specifies required period for core-logic
initiated bus cycle for calibrating I/O buffers.
CAL_CYCLE Period
000 4 ms
001 16 ms
010 64 ms
011 256 ms
100-110 Reserved for future use
111 Calibration Cycle Not Needed
9 R1-IW Reserved
(SBA)
Always returns 1 when read; write operations have no effect.
AGP3.0 devices are required to support side band
addressing, even when operating in AGP 2.0 compatibility
mode.
8 RZ-IW Reserved Always returns 0 when read; write operations have no effect.
7 RZ-IW Reserved Always returns 0 when read; write operations have no effect.
6
MST: RZ-IW
TGT: R-IW-Dx
htrans# TARGET ONLY: When 0, core-logic will translate host processor
accesses through the AGP3.0 aperture using the GART. When 1,
core-logic will not send host processor accesses through the
aperture. Host translation may be required for certain legacy software
support.
5 R-IW-Dx OVER4G
10
MASTER & TARGET: If set, this Master or Target supports
addresses greater than 4 GB.
4 R-IW FW MASTER & TARGET: If set to a 1, this Master or Target
supports Fast Writes. Fast-Write support is optional for both
Master and Target.
3 R-IW AGP3.0_MODE 1 means AGP3.0_Mode. 0 means AGP2.0 Mode. Set on
power
-
up reset. See section 2.4.2 for details. Note that when
10
If Target (Core-Logic) sets OVER4G it must support >32bit address PCI cycles generated by the Master using DAC. See
PCI Local Bus Specification V2.2 for details. However, support of outbound DAC transactions from the core-logic to the
Graphics Card is optional.