Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification

Rev. 1.0

relationship from that of AGP2.0 (e.g. the SBA bits are now SBA#, indicating that a logic 1 is signaled as

a low voltage on the interconnect).

Table 30: AGP3.0 Signals and Associated Clock Domains

Signal Name Clock Domain

Source Synchronous Common Clock Asynchronous USB

**SBA#[7::0]

**RBF

**WBF

ST[2::0]

STBF[1::0]

STBS[1::0]

SB_STBF

SB_STBS

CLK

USB+

USB

OVRCNT#

PME#

TYPEDET#

GC_DET#

MB_DET#

**FRAME

**IRDY

**TRDY

**STOP

**DEVSEL

**PERR

**SERR

**REQ

**GNT

RST#

AD[31::0]

**C#/BE[3::0]

PAR

INTA#, INTB#

Vrefcg, Vrefgc

DBI_HI, DBI_LO

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Signals marked as either Common Clock or Source Synchronous in Table 30 are capable of supporting

533 MT/s interface using a 800 mV swing referenced to ground and a 350 mV input reference voltage.

CLK is the single exception, as it is only a 66MHz signal clock. Its electrical characteristics remain unchanged from the

AGP interface specification.