Accelerated Graphics Port Interface Specification

AGP3.0 Interface Specification
Rev. 1.0
6
3.4.1 AGP3.0 Signaling Details .....................................................................................................63
3.4.2 Signaling Details for Non-AGP3.0 Signals ...........................................................................65
3.5 System Topologies and Specifications ......................................................................................66
3.5.1 Universal AGP3.0 Topologies ..............................................................................................66
3.5.2 Other Topologies..................................................................................................................67
3.5.3 System Level Definitions......................................................................................................67
3.5.4 Motherboard Level Specification..........................................................................................69
3.5.5 Add-in Card Specifications...................................................................................................71
3.5.6 Motherboard / Add-in Card Interoperability...........................................................................73
3.5.7 Reset Requirements for AGP3.0 Universal systems..........................................................74
3.6 Component Level Electrical Specifications ................................................................................77
3.6.1 DC Specs.............................................................................................................................77
3.6.2 AC Measurement and Test Conditions................................................................................78
3.6.3 AC Timings...........................................................................................................................80
3.6.4 Signal Integrity Requirement for AGP3.0 .............................................................................83
3.6.5 Maximum AC Ratings and Device Protection......................................................................86
3.6.6 Driver and Receiver Characteristics....................................................................................88
3.7 Package Considerations.............................................................................................................92
3.7.1 Bump-out/Leadframe Requirements ...................................................................................93
3.7.2 Pin-out/Ball-out Requirements.............................................................................................94
3.8 Power Delivery and Distribution..................................................................................................94
3.8.1 Power Supply Delivery.........................................................................................................94
4 APPENDIX A: WORKSTATION ENHANCEMENTS................................................96
4.1 Isochronous Mode Operation......................................................................................................96
4.1.1 4x Speed and Isochronous Support.....................................................................................97
4.1.2 Contract Parameters ...........................................................................................................97
4.1.3 Transaction Ordering.........................................................................................................100
4.1.4 Guaranteed Global Visibility................................................................................................101
4.1.5 Coherent Isochronous Requests.......................................................................................101
4.1.6 Isochronous Request/Status Encoding.............................................................................102
4.1.7 Identifying Isochronous Data..............................................................................................104
4.1.8 Flow Control.......................................................................................................................104
4.1.9 Isochronous Bridges ..........................................................................................................104
4.1.10 Setting T, L, Y, N for AGP3.0 Core-logic and AGP3.0 Devices......................................105
4.1.11 Time Keeping..................................................................................................................107
4.2 Flow Control Change................................................................................................................108
4.2.1 Isochronous Transactions and Buffer-Full Flow Control...................................................108
4.2.2 AGP3.0 Fast Write Flow Control........................................................................................108
4.3 Synchronization Models............................................................................................................109
4.3.1 Global Visibility....................................................................................................................109
4.3.2 Request Completion ..........................................................................................................109
4.3.3 Write Completion ...............................................................................................................110
4.3.4 Synchronization Case 1: Processor Data to AGP.............................................................110
4.3.5 Synchronization Scheme: Case 2 AGP Data to Processor..............................................111
4.4 Fan-Out Bridge .........................................................................................................................111
5 APPENDIX B: WORKSTATION PROGRAMMING MODEL ...................................113
5.1 System Components................................................................................................................113
5.2 Port and Device Definitions ......................................................................................................114
5.2.1 AGP Master Device Memory Reference............................................................................114
5.2.2 AGP3.0 Port Requirements ...............................................................................................115
5.2.3 Multiple AGP3.0 Ports ........................................................................................................115
5.3 AGP Graphics Aperture ............................................................................................................116