Accelerated Graphics Port Interface Specification

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AGP3.0 Interface Specification

Rev. 1.0

List of Tables

Table 1: AGP Specification Releases......................................................................................................11

Table 2: V2.0- Compatibility .....................................................................................................................13

Table 3: Changes to AGP2.0 in Core Specs...........................................................................................14

Table 4: Changes to AGP2.0 in Appendices A and B.............................................................................15

Table 5: Signal List...................................................................................................................................17

Table 6: AGP3.0 New Signals..................................................................................................................18

Table 7: Signal Calibrations .....................................................................................................................22

Table 8: DBI Implementation Requirements............................................................................................28

Table 9: Summary of Interfaces Based on Function and Agent..............................................................29

Table 10: Summary of PCI Signals Based on Function and Agent.........................................................30

Table 11: Summary of AGP3.0 Signals Based on Function and Agent ..................................................30

Table 12: AGP3.0/AGP2.0 Bus Requests ...............................................................................................33

Table 13: Status Codes ...........................................................................................................................33

Table 14: Buffer Size Requirements Based on RBF Flow Control.........................................................35

Table 15: Motherboard Options................................................................................................................39

Table 16: Graphics Card Options ............................................................................................................40

Table 17: Selecting Platform Mode of Operation.....................................................................................41

Table 18: Supported Speed Description..................................................................................................41

Table 19: Setting Speed of Operation......................................................................................................42

Table 20: PCI Peer-to-Peer Access ........................................................................................................42

Table 21: Register Description ................................................................................................................44

Table 22: Sub-field Values .......................................................................................................................44

Table 23: PCI Register.............................................................................................................................45

Table 24: CAPPTR Capabilities...............................................................................................................45

Table 25: Major/Minor Revisions ..............................................................................................................46

Table 26: Major and Minor Revision ID Selection.....................................................................................46

Table 27: AGP Register ...........................................................................................................................47

Table 28: Command Register..................................................................................................................48

Table 29: AGP3.0 Motherboard Connector Pinout...................................................................................50

Table 30: AGP3.0 Signals and Associated Clock Domains ....................................................................53

Table 31: Common Clock Timing Budget................................................................................................61

Table 32: Source Synchronous Skew Timing Budget.............................................................................62

Table 33 Motherboard Interconnect Requirements

................................................................................70

Table 34: Add-in Card Interconnect Requirements

................................................................................71

Table 35: Motherboard / Add-in Card Interoperability...............................................................................73

Table 36: AGP Target Signal State During and After RESET .................................................................75

Table 37: AGP Master Signal State During and After RESET.................................................................76

Table 38: DC Specifications for AGP3.0 Source Synchronous Signaling...............................................77

Table 39: Measurement and Test Condition Parameters........................................................................79

Table 40: AGP3.0 AC Timing Parameters, 66 MHz Common Clock......................................................80

Table 41: AGP3.0 AC Source-Synchronous Timing Parameters ...........................................................81

Table 42: Input/Output Signal Integrity Requirements .............................................................................86

Table 43: Parameters for Maximum AC AGP3.0 Signaling Waveforms.................................................87

Table 44: Equations for Current Limits on Pull-down Driver and Terminator..........................................88

Table 45: Specifications for AGP3.0 Driver and Terminator....................................................................90

Table 46: Part-to-part and Intra-group Variations.....................................................................................91

Table 47: Add-in Card Power Supply Limits ............................................................................................95

Table 48: Transaction Size Vs Payload Size...........................................................................................98

Table 49: Minimum Isochronous Bandwidth............................................................................................98