Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
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3.4 Clocking for Multiple Codec Implementations
To keep the system synchronous, all Primary and Secondary Codec clocking must be derived from the same clock
source, so they are operating on the same time base. In addition, all AC-link protocol timing must be based on the
BIT_CLK signal, to ensure that everything on the AC-link will be synchronous.
The following are potential 24.576 MHz clock options available to a Secondary Codec:
1.
Using a common external 24.576 MHz signal source (external oscillator or AC ‘97 Digital Controller)
2.
Using the Primary’s crystal out
3.
Using the Primary’s BIT_CLK output to derive 24.576MHz
3.4.1 Primary AC, MC, or AMC Codec
Primary AC/MC/AMC devices are required to support correctly either of the following clocking options:
1.
24.576 MHz crystal attached to XTAL_IN and XTAL_OUT
2.
24.576 MHz external oscillator provided to XTAL_IN
3.
12.288 MHz oscillator provided to the BIT_CLK input
The Primary device may also optionally support the following clocking option:
4.
14.318 MHz external oscillator provided to XTAL_IN
If a modem Codec is configured as the Primary AC-link Codec, there should not be any Audio Codecs residing on
the AC-link (i.e., a modem-only configuration is the only supported configuration for MC ‘97 as the Primary AC-
link Codec).
3.4.2 Secondary AC Codec
Secondary AC devices are required to function correctly using one or more of the following clocking options:
1.
24.576 MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary
24.576MHz clock)
2.
the BIT_CLK input provided by the Primary
3.4.3 Secondary MC Codec
Secondary AC/MC/AMC devices are required to use one or more of the following clocking options to function
correctly:
1.
The BIT_CLK input provided by the Primary
2.
A vendor specified crystal attached to XTAL_IN and XTAL_OUT
3.
24.576 MHz external oscillator provided to XTAL_IN (synchronous with Primary, optionally 3.3Vaux
powered)
Regardless of clocking option, Secondary MC Codecs are required to observe AC-link timing synchronous with
their BIT_CLK and SYNC inputs. Secondary MC Codecs that utilize clocking option (1) during full power states
have a dependency on the accuracy and stability of the BIT_CLK sourced by the Primary AC Codec. Secondary
MC Codecs that support wake-up/Caller-ID functionality depend on option (2) or (3) at least during 3.3Vaux
powered states. The choice of clocking options (2) vs. (3) can have an impact on sleep state power consumption.
3.4.3.1 Special AC + MC considerations
A multiple Codec audio plus modem configuration typically would want to target the highest quality audio while
also supporting D3 cold wake-up modem capabilities. Highest quality audio mandates clean AVdd and DVdd
voltage sources for the audio Codec, while modem power management (D3 wake) capabilities dictates being
powered by Vaux. Given this there may be cases when it makes sense to supply a free running high-speed clock to
both Codecs. In this way all Codecs can be independently power managed without any problems that would be