Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
37
Function Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(Valid Slot 1 Address)
Slot 0, bit 13
(Valid Slot 2 Data)
Slot 0, Bits 1-0
(Codec ID)
AC ‘97 Digital Controller
Primary Read
Frame N, SDATA_OUT
1 1 0 00
AC ‘97 Digital Controller
Primary Write
Frame N, SDATA_OUT
1 1 1 00
AC ‘97 Codec Status
Frame N+1, SDATA_IN
1 1 1 00
Table 11. Primary Codec Addressing: Slot 0 Tag Bits
When the AC ‘97 Digital Controller addresses a Secondary Codec, the Slot 0 Tag bits for Address and Data must be
0. A non-zero, 2-bit Codec ID in the LSBs of Slot 0 indicates a valid Read or Write Address in Slot 1, and the Slot 1
R/W bit indicates presence or absence of valid Data in Slot 2.
Function Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(Valid Slot 1 Address)
Slot 0, bit 13
(Valid Slot 2 Data)
Slot 0, Bits 1-0
(Codec ID)
AC ‘97 Digital Controller
Secondary Read
Frame N, SDATA_OUT
1 0 0 01, 10, or 11
AC ‘97 Digital Controller
Secondary Write
Frame N, SDATA_OUT
1 0 0 01, 10, or 11
AC ‘97 Codec Status
Frame N+1, SDATA_IN
1 1 1 00
Table 12. Secondary Codec Addressing: Slot 0 tag bits
4.5.2 Codec Register Status Reads
The following are AC ‘97 compliance requirements for registers outside of the vendor-defined space (5Ah-7Ah),
and AC ‘97 recommendations for registers within the vendor-defined space. Driver authors should not make any
assumptions about vendor-defined space until they have confirmed the manufacturer and revision (Registers 7Ch-
7Eh) of the Codec being driven.
• Non-implemented Register Bits: All reserved or non-implemented register bits (marked x in the tables) are
required to return 0 when read.
• Non-implemented Addresses: Read access to non-implemented registers are required to echo a ‘valid’ 7-
bit register address in Input Slot 1 and return ‘valid’ 0000h data in Input Slot 2 on the next AC-link frame.
• Odd Register Addresses: Read (and write) access to odd register addresses are required to be treated the
same as non-implemented addresses, instead of aliasing them to the next lower even-numbered register.
4.5.3 Codec Register Status Read Completion Latency
For maximum Controller/Codec interoperability AC ‘97 compliance requires that Codec register read data be
returned in the next AC-link frame following the frame in which the read request occurs.