Audio Codec '97
AC ‘97 Component Specification Revision 2.3 Rev 1.0
5
5.8 EXTENDED AUDIO REGISTER SET.................................................................................................................57
5.8.1 Extended Audio ID Register (Index 28h) .............................................................................................57
5.8.2 Extended Audio Status and Control Register (Index 2Ah) ...................................................................58
5.8.3 Audio Sample Rate Control Registers (Index 2Ch – 34h)....................................................................60
5.8.4 Surround and Center/LFE Volume Control Registers (Index 36h and 38h)........................................60
5.8.5 S/PDIF Control Register (Index 3Ah)..................................................................................................61
5.8.6 Vendor Reserved Registers (Index 5Ah - 5Fh, 70h - 7Ah)...................................................................62
5.8.7 Extended Codec Registers Page Structure Definition..........................................................................62
5.8.7.1 Extended Registers Page 00............................................................................................................................. 62
5.8.7.2 Extended Registers Page 01............................................................................................................................. 62
5.8.7.3 Extended Registers Page 02-0Fh...................................................................................................................... 62
5.8.8 Vendor ID Registers (Index 7Ch - 7Eh)...............................................................................................62
5.9 EXTENDED CODEC REGISTERS PAGE ‘01’ ....................................................................................................63
5.9.1 Discovery Descriptor Definition..........................................................................................................63
5.9.2 Audio Input/Output Capabilities Register............................................................................................64
5.9.2.1 Function Select Register (Index 66h)............................................................................................................... 65
5.9.2.2 Information and I/O Register (Index 68h)........................................................................................................ 65
5.9.2.3 Sense Register (Index 6Ah).............................................................................................................................. 67
5.9.3 Slot Mapping Descriptor .....................................................................................................................69
5.10 S/PDIF CONCURRENCY ................................................................................................................................70
5.10.1 Required concurrency support for S/PDIF transmission (48 kHz operation) .....................................71
5.10.1.1 Simultaneous DAC playback and S/PDIF transmission of a single 2-ch 48 kHz PCM stream.................... 71
5.10.1.2 Simultaneous DAC playback of a 2-ch 48 kHz PCM stream and S/PDIF transmission of an independent 48
kHz PCM or encoded multichannel stream ....................................................................................................................... 71
5.10.1.3 Secondary Codec supports simultaneous DAC playback of a 2-ch 48 kHz PCM stream and S/PDIF
transmission of an independent 48 kHz PCM or encoded multichannel stream ................................................................ 72
5.10.1.4 Primary or Secondary codec supports independent S/PDIF transmission of PCM or encoded stream on slots
10&11 ..................................................................................................................................................................... 72
5.10.2 Optional support for rates other than 48 kHz......................................................................................72
5.10.2.1 Simultaneous DAC playback and S/PDIF transmission of a single 2-ch non 48 kHz PCM stream............. 72
5.10.2.2 Simultaneous DAC playback and S/PDIF transmission of “bit exact” 32, 44.1, or 48 kHz PCM streams .. 72
6. Modem AFE Features .......................................................................................................................................73
6.1 OVERVIEW....................................................................................................................................................73
6.2 SLOT ASSIGNMENTS FOR MODEM ................................................................................................................73
6.3 GPIO PIN DEFINITIONS ................................................................................................................................74
6.3.1 GPIO Pin Implementation ...................................................................................................................74
6.3.2 Recommended Slot 12 GPIO Bit Definitions .......................................................................................75
6.4 MODEM CODEC COST REDUCTION OPTIONS ................................................................................................76
6.4.1 Elimination of the On-board Modem Speaker .....................................................................................76
6.4.2 Internal PHONE and MONO_OUT Connections (AMC ‘97 ) ............................................................76
6.5 WAKE-UP AND POWER MANAGEMENT EVENT (PME#) SUPPORT.................................................................77
6.5.1 Combined Audio/Modem AFE Codec (AMC ‘97 )...............................................................................77
6.5.2 Split Partitioned Implementations (AC ‘97 + MC ‘97 ) .....................................................................79
6.5.3 Wake-up and Voltage Sequencing .......................................................................................................79
6.5.4 Wake-up and Caller ID Decode in the Controller and/or Codec ........................................................79
6.6 MODEM AFE REGISTER DEFINITIONS ..........................................................................................................80
6.6.1 Extended Modem ID Register (Index 3Ch) ..........................................................................................80
6.6.2 Extended Modem Status and Control Register (Index 3Eh) ................................................................81
6.6.3 Modem Sample Rate Control Registers (Index 40h – 44h)..................................................................82
6.6.4 Modem DAC/ADC Level Control Registers (Index 46h – 4Ah)...........................................................83
6.6.5 GPIO Pin Configuration Register (Index 4Ch) ...................................................................................83
6.6.6 GPIO Pin Polarity/Type Register (Index 4Eh) ....................................................................................83
6.6.7 GPIO Pin Sticky Register (Index 50h) .................................................................................................83
6.6.8 GPIO Pin Wake-up Mask Register (Index 52h)...................................................................................84
6.6.9 GPIO Pin Status Register (Index 54h).................................................................................................84
6.6.10 Miscellaneous Modem AFE Status and Control Register (Index 56h) ................................................84
6.7 LOOPBACK MODES FOR TESTING ..................................................................................................................85