Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0

A CODEC indicates that it does not support a given DAC or ADC by having a read only value of 0000b in the bits

associated with the unsupported DAC or ADC.

The MV bit is used to indicate that page 01 offsets 6Ch and 6Eh should be used to steer the slot to DAC/ADC

mappings, rather than the DSA[1:0] bits in the Extended Audio ID register 28h. This bit defaults to zero, meaning

that the DSA[1:0] bits and the AMAP defaults determine the slot to DAC/ADC mappings. When the software

programs values into the DAC Slot Mapping Register or the ADC Slot Mapping Register, it must then set this bit to

a “1” to cause the values in these registers to override the DSA[1:0] bits. A read only value of “0” for this bit

indicates that the codec does not support this re-mapping capability. All other values should also be “0”.

If the codec has the capability to reassign which slots are decoded, then it must implement the above registers as

R/W registers. If the codec does not have this capability, the registers must be implemented as read only with value

“00h”. If any of the codec’s slot to DAC mappings are implemented as remappable, all must be remappable. If any

of the codec’s slots to ADC mappings are implemented as remappable, all must be remappable.

If a codec supports a given DAC or ADC, then the software indicates that the DAC or ADC should decode a

different slot or set of slots by programming a different value into the register. Software may indicate that the DAC

or ADC is not being used by programming a value of 0h into the associated slot mapping register. This indicates

that no slots should be associated with the DAC/ADC. The DAC or ADC should be treated as unused, and the

associated output muted. Volume, mute, and other registers associated with the DMA engine should continue to

behave normally, but will have no effect.

In the case of a mono DAC/ADC, the second slot in the pair is not used. No data is sent, and the Slot Valid bits are

not enabled.

Software is responsible for making sure that the slots specified are compatible with the controller; for instance, some

controllers may not be able to accept a stream from a mono ADC on a slot which the controller has implemented as

part of a stereo DMA engine.

Valid Values for Slot Mapping Registers

Value Slots used by DAC/ADC

3h Slots 3,4 (Slot 3 for mono)

6h Slots 6,9 (Slot 6 for mono)

7h Slots 7,8 (Slot 7 for mono)

Ah Slots 10,11 (Slot 10 for mono)

0h None/Not implemented

1,2,4,5,8,9,B,C,D,E,F Reserved

Table 38. Register Values for Slot Mapping Registers

Note that the S/P-DIF output slot reassignment is controlled by the SPSA[1:0] of the Extended Audio Status and

Control Register (Index 2Ah), and is independent of the definition of these registers and the operation of the DAC

and ADC slot remapping.

5.10 S/PDIF Concurrency

A S/PDIF capable Codec must support concurrent DA conversion and S/PDIF transmission. But this capability is

dependent upon a number of factors

• The format may be PCM, or non-PCM

• The source data may be shared, or independent

• PCM data may already be playing, restricting S/PDIF transmitter AC-link slot or rate options

• S/PDIF data may already be playing, restricting PCM DA conversion AC-link slot or rate options

• The slot assignment may be shared, or independent