Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
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then low. PME# is cleared out in the AC ‘97 Digital Controller by system software, asynchronous to AC-link
activity. The AC ‘97 Digital Controller must always monitor the Codec’s ready bit before sending data to it.
6.5.2 Split Partitioned Implementations (AC ‘97 + MC ‘97 )
In a split partitioned implementation, where separate audio and modem AFE Codecs are employed, the MC ‘97
Codec, its DAA, a common clock oscillator, and portions of the AC ‘97 Digital Controller are powered by Vaux.
The AC ‘97 audio-only Codec is powered via its normal DVdd, and AVdd supplies, and as such is shut completely
off when the system enters a sleeping state. Figure 25 shows an example of a split partitioned Codec
implementation.
Digital
Controller
MC '97
Secondary Codec
AC '97
Primary codec
SDATA_OUT
SDATA_IN(0)
SDATA_IN(1)
DAA
BIT_CLK
Powered by Vaux
PME#
OSC
Vaux
Vdd
SYNC
RESET#
Figure 25. Split Partitioned Design Example
Once the system enters a sleeping state Vdd shuts off, which causes the oscillator input to the AC ‘97 to go low and
remain low. Clocking remains active at the MC ‘97, which continues to look for ring detection and Caller ID data
while the rest of the system sleeps. A wake or power management event causes the MC ‘97 to transition its
SDATA_IN from low to high, which in turns causes the AC ‘97 Digital Controller to assert PME# to the system.
Once the main power has been reapplied the device driver executes a cold or warm AC-link reset followed by the
restoration of any saved off- functional context. Following SDATA_IN’s low-to-high transition as a result of a
Power Management event, it must remain high until either a warm or cold reset is observed on the AC-Link.
6.5.3 Wake-up and Voltage Sequencing
AC ‘97 Codecs have both analog and digital supply pins defined. There are no voltage sequencing requirements for
AVdd and DVdd specifying which voltage source ramps up or down first.
In an “Always Ready, Power Management”-capable PC the main Vdd voltage rails will be shut off under program
control in order to achieve a very low power state, yet remain connected. Auxiliary power (Vaux), will remain active
in the system to keep portions of the modem “alive”
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. Codec designs that support separate voltage inputs for
analog and digital sections must comprehend this so that no device damage or malfunction can occur as a result of
the main voltage dropping off while the auxiliary supply remains active.
6.5.4 Wake-up and Caller ID Decode in the Controller and/or Codec
The resume time for a PC in D3 low power state makes it unlikely that a driver will completely load in time to
wake-up the AC ‘97 Digital Controller and enable it to capture Caller ID data on the line. Therefore either the AC
‘97 Digital Controller or (A)MC ‘97 Codec must be able to store this information while the driver continues to
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This includes all logic required to detect the external wake event, and then to report it across the AC-link.