Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
89
resume latency, etc., is available in the Microsoft Communications Device Class Power Management Reference
Specification** located at:
http://www.microsoft.com/hwdev/download/compmspc.rtf
Table 45 details a lower-level mapping of the modem subsystem D states to the recommended MC ‘97 Codec power
savings PR settings.
PR<A:D> + MLNK
(1-line modem Codec example)
+12
Vmai
n
+5Vaa
from
+12Vmai
n
+3.3
Vmai
n
+3.3
Vaux
Comments
AC-Link DAC1 ADC1 Vref GPIO
Device State MLNK D C B A
D0 0 0 0 0 0 On On On On All on
D1 0 1 1 0 0 On On On On -DAC, -ADC
D2 0 1 1 0 0 On On On On Same as D1
D3
hot
1
Note 1
1 1 Note 2
Note 2 On On On On -AC-Link
D3
cold
- - - Note 2 Note 2 Off Off Off On 3.3Vaux power
only
Table 45. Recommended Modem Codec D state to PR bit mapping
Note 1: Codec behavior, with respect to the setting of its MLNK bit, is dependent upon whether the modem Codec
was configured as the Primary or Secondary Codec. Refer to Section 7.3 below.
Note 2: GPIO (PRA) bit must be 0 to enable wake-on-ring functionality. If caller ID is supported, to enable caller ID
capture, the Vref (PRB) bit must also be 0.
7.3 Power Management with Wake-up Capabilities
7.3.1 Primary MC’97 Codec and MLNK
Setting the MLNK bit must result in an AC-link halt condition (BIT_CLK stays at a logic low level). At the same
time the modem Codec must also drive and hold its SDATA_IN signal low. This is similar to setting the PR4 bit for
a Primary AC ‘97 audio Codec.
Once the MLNK bit has been set by its modem driver, BIT_CLK and SDATA_IN must remain at a logic low level
until one of three events happen:
1.
Low to high transition of RESET# on the AC-link
2.
Warm Reset sequence signaled on the AC-link
3.
A power management event occurs, such as a ring detection (pertains to SDATA_IN only)
The low to high transition of AC-link RESET# indicates resumption from the D3
cold
state where AC-link power had
been removed. The sampling of this transition on the RESET# signal must effectively be treated as if observing a
warm reset in the sense that no internal auxiliary powered state logic is impacted (i.e., reinitialized). Unaffected
logic must include, but not necessarily be limited to, wake event status and caller ID data if supported. Resumption
of normal AC-link activity must begin as though the Codec had been issued a warm reset semantic.
Warm Reset is the required resume sequence when the modem Codec has been resumed from a D3
hot
state where
the AC-link had been halted yet full power had been maintained. If the modem Codec observes a Warm Reset
sequence (i.e., SYNC assertion in the absence of BIT_CLK) the modem Codec shall reactivate the AC-link in the
manner specified in Section 3.6.2.