Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
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that are shut off when the PC enters an ACPI sleep state of S3, S4 or S5. Additionally it enables the modem Codec
to power its wake logic when in an S3, S4 or S5 ACPI sleep state.
7.5.3 AMC ‘97 (Primary) Implementations
The AMC ‘97 combination Codec must implement the same power distribution strategy as for the split partitioned
AC + MC Codec configuration. This imposes a requirement on AMC ‘97 Codec designs, in that they are designed
with split power wells enabling multi-voltage power distribution for different sections of the component. Please
refer to Table 50.
7.6 AC + MC clocking considerations
In an AC ‘97 compliant multiple audio + modem Codec configuration
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the AC ‘97 Digital Controller and
Secondary modem Codec depend upon the Primary audio Codec delivering BIT_CLK to them for proper modem
operation.
Therefore when the modem is in the active state (i.e., D0) the audio driver must never shut off the BIT_CLK by
setting the audio Codec PR4 bit. In addition, the audio and modem drivers must be mutually exclusive of each
other, meaning that the audio driver is limited to managing the audio Codec hardware only and must not interact
directly with the modem driver or modem Codec hardware. To avoid this BIT_CLK clocking issue it is
recommended that the audio Codec PR4 bit NOT be set in multiple audio + modem Codec configurations.
AC ‘97 Multiple Codec Clocking Recommendations:
1. An audio driver should never set the PR4 bit in a multiple audio + modem Codec configuration. This
ensures that the BIT_CLK never stops when the PC is in the working state.
2.
Primary Codecs should implement the following clocking options:
a.
Using an external 24.576MHz crystal between the XTAL_IN and XTAL_OUT pins.
b.
An external oscillator signal present on XTAL_IN with support for 14.318MHz or 24.576
MHz frequencies.
c.
An external oscillator input of frequency 12.288MHz on BIT_CLK.
All of the above cases (a-c) must result in BIT_CLK running at 12.288MHz.
3.
Secondary Codecs use BIT_CLK (and SYNC) input for all AC-link transaction timings
4.
Secondary modem Codecs should support an additional, auxiliary powered clock input (XTAL or
OSC) that is used for hardware caller ID functionality while the system is in an ACPI S3, S4 or S5
sleep state (i.e., for use at times when the AC-link, including BIT_CLK, is powered off)
Audio-only multiple Codec implementations should have no BIT_CLK clocking issues as all of the AC-link Codecs
are managed by the same device driver.
7.7 Resume Latency: Device Driver Considerations
Device drivers should be written to distinguish between a cold boot, and a resume event from S3, S4 or S5. By
making this distinction a driver could be written to minimize its contribution to the system’s resume latency.
Device drivers should not use the same boot time initialization code sequence when resuming from S3, S4, or S5
sleep states.
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An AC ’97 audio Codec with a physically separate MC ’97 modem Codec or, a combined AMC ’97 audio/modem
Codec.