Audio Codec '97

AC ‘97 Component Specification Revision 2.3 Rev 1.0
99
Parameter Symbol Min Typ Max Units
SYNC active high pulse
width
T
sync_high
1.0 - - µs
SYNC inactive to BIT_CLK
startup delay
T
sync2clk
162.8 - - ns
Table 54. Warm Reset timing parameters
Please note that this minimum SYNC pulse width pertains to warm reset only, during normal operation SYNC is
asserted for the entire tag phase (16 BIT_CLK times).
9.2.2 AC-link Clocks
Figure 32. BIT_CLK and SYNC Timing diagram
Parameter Symbol Min Typ Max Units
BIT_CLK frequency - 12.288 - MHz
BIT_CLK period Tclk_period - 81.4 - ns
BIT_CLK output jitter - - 750 ps
BIT_CLK high pulse width (note 2) Tclk_high 36 40.7 45 ns
BIT_CLK low pulse width (note 2) Tclk_low 36 40.7 45 ns
SYNC frequency - 48.0 - kHz
SYNC period Tsync_perio
d
- 20.8 - µs
SYNC high pulse width Tsync_high - 1.3 - µs
SYNC low pulse width Tsync_low - 19.5 - µs
Note 1: 47.5-75 pF external load as per Table 62
Note 2: Worst case duty cycle restricted to 45/55
Table 55. BIT_CLK and SYNC Timing Parameters