Intel® Core™2 Extreme Processor QX9775Δ Datasheet February 2008 Document Number:319128-001
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Contents 1 Introduction................................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 References ....................................................................................................... 12 2 Electrical Specifications ...............................................................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 5-1 5-2 5-3 5-4 5-5 6-1 Input Device Hysteresis.............................................................................................23 Processor Load Current versus Time............................................................................27 Processor VCC Static and Transient Tolerance Load Lines ..............................................29 VCC Overshoot Example Waveform .......................................................
Revision History Revision -001 Datasheet Description Initial release Date February 2008 5
Datasheet
Intel® Core™2 Extreme Processor QX9775Δ Features • Intel® Intelligent Power Capability • Intel® Advanced Digital Media Boost • Optimized for 32-bit applications running on advanced 32-bit operating systems • Available at 3.
Datasheet
Introduction 1 Introduction The Intel® Core™2 Extreme processor QX9775 is a server/workstation processor using four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Intel® Core™2 Extreme processor QX9775 maintains the tradition of compatibility with IA-32 software.
Introduction The processor is intended for high performance server and workstation systems. The processor supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. The processor is packaged in an FC-LGA Land Grid Array package with 771 lands for improved power delivery.
Introduction • • • • • • • • • • • • • • • Datasheet two processor agents. The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. Functional Operation – Refers to the normal operating conditions in which all processor specifications, including DC, AC, FSB, signal quality, mechanical and thermal are satisfied. Storage Conditions – Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document Location Intel® Core™2 Extreme Processor QX9775 Specification Update http://www.intel.com/ design/processor/ specupdt/319129.htm Intel® Core™2 Extreme Processor QX9775 Thermal and Mechanical Design Guidelines Addendum (TMDG) http://www.intel.com/ design/processor/ designex/319130.htm LGA771 Socket Mechanical Design Guide http://www.intel.
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most processor FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Electrical Specifications 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor.
Electrical Specifications 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT, and are used to select the FSB frequency. Refer to Table 2-14 for DC specifications. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination.
Electrical Specifications 2.5 Voltage Identification (VID) The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to VTT. Refer to Table 2-15 for the DC specifications for these signals.
Electrical Specifications Table 2-3. Voltage Identification Definition HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX HEX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.2750 72 1 1 1 0 0 1 0.9000 34 0 1 1 0 1 0 1.2875 70 1 1 1 0 0 0 0.
Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 Description 0 0 Reserved 0 1 Intel® Core™2 Extreme processor QX9775 1 0 Reserved 1 1 Reserved NOTE: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. Table 2-5.
Electrical Specifications 2.7 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Signals1 Type TAP Input Synchronous to TCK TCK, TDI, TMS, TRST# TAP Output Synchronous to TCK TDO Power/Other COMP[3:0], GTLREF_ADD_MID, GTLREF_ADD_END, GTLREF_DATA_MID, GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0], PECI, RESERVED, SKTOCC#, TESTIN1, TESTIN2, TESTHI[12:10], VCC, VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL, VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2, VSS, VTT, VTT_OUT, VTT_SEL Power/Other NOTES: 1.
Electrical Specifications Table 2-9. Signal Reference Voltages GTLREF A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#,BPRI#, BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY# 2.
Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Vin Vhysteresis Definition and Conditions Input Voltage Range Hysteresis Min Max Units -0.150 VTT V 0.1 * VTT N/A V Notes1 Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V -6.0 N/A mA 0.5 1.0 mA N/A 50 µA 2 N/A 10 µA 2 N/A 10 pF 3 0.
Electrical Specifications 2.11 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.
Electrical Specifications Table 2-11. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit VCC Core voltage with respect to VSS -0.30 1.35 V VTT FSB termination voltage with respect to VSS -0.30 1.45 V TCASE Processor case temperature See Chapter 5 See Chapter 5 °C TSTORAGE Storage temperature -40 85 °C Notes1, 2 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2.
Electrical Specifications Table 2-12. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit VID range 0.850 — 1.3500 V VID VCC Processor Number: VCC for processor core QX9775 3.2 GHz See Table 2-13 and Figure 2-3 Notes 1, 10 V 2, 3, 4, 8, 18 2 Vcc_boot Default VCC Voltage for initial power up — 1.10 — V VVID_STEP VID step size during a transition — — ± 12.
Electrical Specifications 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Figure 5-1. This specification refers to the total reduction of the load line due to VID transitions below the specified VID. Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings. This specification applies to the VCCPLL land.
Electrical Specifications Table 2-13. Processor VCC Static and Transient Tolerance ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.010 VID - 0.020 1,2,3 5 VID - 0.006 VID - 0.016 VID - 0.026 1,2,3 10 VID - 0.013 VID - 0.023 VID - 0.033 1,2,3 15 VID - 0.019 VID - 0.029 VID - 0.039 1,2,3 20 VID - 0.025 VID - 0.035 VID - 0.045 1,2,3 25 VID - 0.031 VID - 0.041 VID - 0.051 1,2,3 30 VID - 0.038 VID - 0.048 VID - 0.058 1,2,3 35 VID - 0.044 VID - 0.
Electrical Specifications Figure 2-3. Processor VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID - 0.000 VID - 0.050 VCC Maximum Vcc [V] VID - 0.100 VID - 0.150 VCC Typical VCC Minimum VID - 0.200 VID - 0.250 Table 2-14. AGTL+ Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 0 GTLREF–0.10 V 2,4,6 VIL Input Low Voltage -0.
Electrical Specifications Table 2-15. CMOS Signal Input/Output Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 V 2,6 VIL Input Low Voltage -0.10 0.00 0.3 * VTT VIH Input High Voltage 0.7 * VTT VTT VTT + 0.1 V 2 VOL Output Low Voltage -0.10 0 0.1 * VTT V 2 VOH Output High Voltage 0.9 * VTT VTT VTT + 0.1 V 2 IOL Output Low Current 1.70 N/A 4.70 mA 3 IOH Output High Current 1.70 N/A 4.
Electrical Specifications Figure 2-4. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.13.
Electrical Specifications 2.14 AGTL+ FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design. In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-8 for details on which signals do not include on-die termination. Refer to Table 2-18 for RTT values.
Electrical Specifications Table 2-19. FSB Differential BCLK Specifications Symbol Notes1 Parameter Min Typ Max Unit Figure VL Input Low Voltage -0.150 0.0 0.150 V 2-5 VH Input High Voltage 0.660 0.710 0.850 V 2-5 VCROSS(abs) Absolute Crossing Point 0.250 0.350 0.550 V 2-5, 2-6 2,9 VCROSS(rel) Relative Crossing Point 0.250 + 0.5 * (VHavg – 0.700) N/A 0.550 + 0.5 * (VHavg – 0.700) V 2-5, 2-6 3,8,9,11 Δ VCROSS Range of Crossing Points N/A N/A 0.
Electrical Specifications Figure 2-5. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-6. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.
Mechanical Specifications 3 Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 3) NOTE: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines (See Section 1.2).
Mechanical Specifications Figure 3-3.
Mechanical Specifications Figure 3-4.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Shear Tensile Torque Units 311 N 70 lbf 111 N 25 lbf 3.95 N-m 35 LBF-in Notes 1,4,5 2,4,5 3,4,5 NOTES: 1.
Mechanical Specifications 3.8 Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram aids in the identification of the processor. Figure 3-5. Processor Top-side Markings (Example) INTEL(M) © ’06 QX9775 INTEL® CORE™ 2 EXTREME SXXX XXXXX 3.
Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-6 and Figure 3-7 show the top and bottom view of the processor land coordinates, respectively. The coordinates are referred to throughout the document to identify processor lands. Figure 3-6.
Mechanical Specifications Figure 3-7.
Mechanical Specifications 44 Datasheet
Land Listing and Signal Description 4 Land Listing and Signal Description 4.1 Land Listing Table 4-1 is a listing of all processor lands ordered alphabetically by Land name. Table 4-2 is a listing of all processor lands ordered by land number.
Land Listing and Signal Description Table 4-1. Land Name 46 Land Listing by Land Name (Sheet 1 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 2 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name Datasheet Land Listing by Land Name (Sheet 3 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 4 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name 48 Land Listing by Land Name (Sheet 5 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 6 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name Datasheet Land Listing by Land Name (Sheet 7 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 8 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name 50 Land Listing by Land Name (Sheet 9 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 10 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name Datasheet Land Listing by Land Name (Sheet 11 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 12 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name 52 Land Listing by Land Name (Sheet 13 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 14 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name Datasheet Land Listing by Land Name (Sheet 15 of 17) Land No. Signal Buffer Type Direction Table 4-1. Land Name Land Listing by Land Name (Sheet 16 of 17) Land No.
Land Listing and Signal Description Table 4-1. Land Name 54 Land Listing by Land Name (Sheet 17 of 17) Land No.
Land Listing and Signal Description Table 4-2. Pin No. Datasheet Land Listing by Land Number (Sheet 1 of 17) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. 56 Land Listing by Land Number (Sheet 3 of 17) Pin Name Signal Buffer Type D8 D12# Source Sync D9 VSS Power/Other D10 D22# Source Sync D11 D15# Source Sync D12 VSS Power/Other D13 D25# Source Sync Direction Input/Output Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. 58 Land Listing by Land Number (Sheet 7 of 17) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. Datasheet Land Listing by Land Number (Sheet 9 of 17) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. 60 Land Listing by Land Number (Sheet 11 of Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. Datasheet Land Listing by Land Number (Sheet 13 of Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No. 62 Land Listing by Land Number (Sheet 15 of Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing and Signal Description Table 4-2. Pin No.
Land Listing and Signal Description 4.2 Signal Definitions Table 4-1. Signal Definitions (Sheet 1 of 11) Name A[37:3]# Type I/O Description A[37:3]# (Address) define a 238-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]# are protected by parity signals AP[1:0]#.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 2 of 11) Name AP[1:0]# BCLK[1:0] Type Description Notes I/O AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[37:3]#, and the transaction type on the REQ[4:0]# signals. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 3 of 11) Name BPM5# BPM4# BPM3# BPM[2:1]# BPM0# Type I/O O I/O O I/O Description Notes BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all FSB agents.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 4 of 11) Name Type Description Notes D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 5 of 11) Name DBSY# DEFER# DP[3:0]# DRDY# Type Description Notes I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor FSB agents.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 6 of 11) Name Type Description Notes FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 7 of 11) Name IGNNE# Type I Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floatingpoint instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 8 of 11) Name Type Description Notes MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# I/O • • • • Enabled or disabled. Asserted, if configured, for internal errors along with IERR#.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 9 of 11) Name RESET# Type I Description Asserting the RESET# signal resets all processors to known states and invalidates their internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 10 of 11) Name Type Description TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO O TDO (Test Data Out) transfers serial test data out of the processor.
Land Listing and Signal Description Table 4-1. Signal Definitions (Sheet 11 of 11) Name Type Description O VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance connection to the processor core power and ground. This signal should be connected to the voltage regulator feedback signal, which insures the output voltage (that is, processor voltage) remains within specification. O VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC).
Thermal Specifications 5 Thermal Specifications 5.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications details on this feature, refer to Section 5.2. Thermal Monitor 1 and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications. Table 5-1. Processor Thermal Specifications Core Frequency Maximum Power (W) Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 155 150 5 See Figure 5-1; Table 5-2 1,2,3,4,5 QX9775 NOTES: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications Table 5-2. 5.1.2 Processor Thermal Profile Table Power (W) TCASE_MAX (°C) Power (W) TCASE_MAX (°C) 0 35.0 80 50.0 5 35.9 85 50.9 10 36.9 90 51.8 15 37.8 95 52.8 20 38.7 100 53.7 25 39.7 105 54.6 30 40.6 110 55.6 35 41.5 115 56.5 40 42.5 120 57.4 45 43.0 125 58.4 50 44.4 130 59.3 55 45.3 135 60.2 60 46.2 140 61.2 65 47.2 145 62.1 70 48.1 150 63.0 75 49.
Thermal Specifications Figure 5-2. Case Temperature (TCASE) Measurement Location NOTE: Figure is not to scale and is for reference only. 5.2 Processor Thermal Features 5.2.1 Intel® Thermal Monitor Features The processor provides two thermal monitor features — Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The Thermal Monitor and Enhanced Thermal Monitor must both be enabled in BIOS for the processor to be operating within specifications.
Thermal Specifications When the TM1 is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 – 50%). Cycle times are processor speed dependent and will decrease as processor core frequencies increase.
Thermal Specifications voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-3 for an illustration of this ordering. Figure 5-3.
Thermal Specifications PROCHOT# is designed to assert at or a few degrees higher than maximum TCASE when dissipating TDP power, and cannot be interpreted as an indication of processor case temperature. This temperature delta accounts for processor package, lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum TCASE when dissipating TDP power.
Thermal Specifications Figure 5-4.
Thermal Specifications 5.3.1.1 TCONTROL and TCC Activation on PECI-based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative.
Thermal Specifications 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The PECI device address for socket 0 is 30h and socket 1 is 31h. Note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Control Interface (PECI) Specification. 5.3.2.2 PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The system can generate a STPCLK# while the processor is in the HALT state. When the system deasserts STPCLK#, the processor will return execution to the HALT state. While in HALT state, the processor will process front side bus snoops and interrupts. 6.2.2.2 Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS.
Features RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 6.2.4.1). While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state.
Features 6.3 Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled.
Features 90 Datasheet
