2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 1 Supporting Intel® Core™ i7, i5, and i3 Desktop Processor Series Supporting Intel® Pentium® Processor G800 and G600 Series Supporting Intel® Celeron® Processor G500 and G400 Series This is Volume 1 of 2 June 2013 Document Number: 324641-008
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Contents 1 Introduction .............................................................................................................. 9 1.1 Processor Feature Details ................................................................................... 11 1.1.1 Supported Technologies .......................................................................... 11 1.2 Interfaces ........................................................................................................ 11 1.2.
2.5 2.6 2.4.1.2 3D Pipeline ...............................................................................29 2.4.1.3 Video Engine ............................................................................30 2.4.1.4 2D Engine ................................................................................30 2.4.2 Processor Graphics Display ......................................................................31 2.4.2.1 Display Planes .......................................................................
4.3 4.4 4.5 4.6 4.7 4.2.5.1 Package C0 .............................................................................. 51 4.2.5.2 Package C1/C1E ....................................................................... 51 4.2.5.3 Package C3 State...................................................................... 52 4.2.5.4 Package C6 State...................................................................... 52 Integrated Memory Controller (IMC) Power Management ........................................
7.11.3 Input Device Hysteresis ...........................................................................87 8 Processor Pin and Signal Information ......................................................................89 8.1 Processor Pin Assignments ..................................................................................89 9 DDR Data Swizzling................................................................................................
6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 8-1 9-1 9-2 Error and Thermal Protection Signals ......................................................................... 67 Power Sequencing Signals........................................................................................ 67 Processor Power Signals .......................................................................................... 68 Sense Signals..............................................................
Revision History Revision Number 001 Revision Date Description January 2011 Initial release • Added Intel® Core™ i5-2405S, i5-2310, and i3-2105 processors 002 • Added Intel® Pentium® processor family desktop – Intel® Pentium® G850, G840, G620, and G620T processors May 2011 • Added Intel® Core™ i5-2320, i3-2125, i3-2130, and i3-2120T processors 003 • Added Intel® Celeron® processor family desktop – Intel® Celeron G540, G530, G530T, and G440 processors September 2011 • Added Intel® Pentium® G860, G
Introduction 1 Introduction The 2nd Generation Intel® Core™ processor family desktop, Intel® Pentium® processor family desktop, and Intel® Celeron® processor family desktop are the next generation of 64-bit, multi-core desktop processor built on 32- nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH).
Introduction Figure 1-1. Desktop Platform System Block Diagram Example DDR3 PCI Express* 2.0 1 x16 or 2x8 Discrete Graphics (PEG) Processor PECI Intel® Flexible Display Interface DMI2 x4 Serial ATA Intel® Management Engine Digital Display x 3 USB 2.0 Platform Controller Hub (PCH) LVDS Flat Panel Intel® HD Audio Analog CRT PCI SPI Flash x 2 SMBUS 2.0 SPI Controller Link 1 FWH LPC 8 PCI Express* 2.
Introduction 1.1 Processor Feature Details • Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.
Introduction • Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices) • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT • Intel® Fast Memory Access (Intel® FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.2.2 PCI Express* • PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Processor with desktop PCH supported configurations Table 1-1.
Introduction • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Introduction 1.2.4 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master. The processors support the PECI 3.0 Specification. 1.2.5 Processor Graphics • The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption.
Introduction 1.3 Power Management Support 1.3.1 Processor Core • Full support of Advanced Configuration and Power Interface (ACPI) C-states as implemented by the following processor C-states — C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology 1.3.2 System • S0, S3, S4, S5 1.3.3 Memory Controller • Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) • Dynamic power-down 1.3.4 PCI Express* • L0s and L1 ASPM power management capability 1.3.
Introduction 1.5 Package • The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155). Note: See the 2nd Generation Intel® Core™ Processor, Intel® Pentium® Processor, and Intel® Celeron® Processor, and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on package. 1.6 Terminology Table 1-2.
Introduction Table 1-2. Terminology (Sheet 2 of 2) Term PCH Description Platform Controller Hub. The new, 2009 chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. PECI Platform Environment Control Interface PEG PCI Express* Graphics. External Graphics using PCI Express* Architecture.
Introduction 1.7 Related Documents Refer to Table 1-3 for additional information. Table 1-3. Related Documents Document Document Number/ Location 2nd Generation Intel® Core™ Processor Family Desktop, Intel®Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 2 http://download.intel.com/design /processor/datashts/324642.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependant on the PCH SKU in the target platform. Refer to Chapter 1 for supported memory configuration details.
Interfaces Table 2-1.
Interfaces 2.1.2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: • tCL = CAS Latency • tRCD = Activate Command to READ or WRITE Command delay • tRP = PRECHARGE Command Period • CWL = CAS Write Latency • Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks.
Interfaces Figure 2-1. Intel® Flex Memory Technology Operation TO M C N o n in t e r le a v e d access B C Dual channel in te r le a v e d a c c e s s B B CH A CH B B B – T h e la rg e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o ry m o d u le C – T h e re m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la rg e r s iz e m e m o ry m o d u le 2.1.3.2.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1 for details. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.
Interfaces handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-3. Packet Flow through the Layers Framing Sequence Number Header Data ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4.
Interfaces 2.2.4 PCI Express* Lanes Connection Figure 2-5 demonstrates the PCIe lanes mapping. Figure 2-5. PCI Express* Typical Operation 16 lanes Mapping 0 1 2 3 4 5 0 2.
Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH. Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal.
Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: • Up to 12 Execution units (EUs) • Hierarchal-Z • Video quality enhancements 2.4.1.1 3D Engine Execution Units • Supports up to 12 EUs.
Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible.
Interfaces 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • DisplayPort and Intel FDI Figure 2-7. Processor Display Block Diagram 2.4.2.
Interfaces 2.4.2.1.4 Video Graphics Array (VGA) VGA is used for boot, safe mode, legacy games, etc. It can be changed by an application without OS/driver notification, due to legacy requirements. 2.4.2.2 Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed. This is clocked by the Display Reference clock inputs.
Interfaces 2.5 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (processor) and a PECI master. The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master. • Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 2.6 Interface Clocking 2.6.1 Internal Clocking Requirements Table 2-4.
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Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Technologies 3.1.
Technologies 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features The processor supports the following Intel VT-d features: • Memory controller and Processor Graphics comply with Intel® VT-d 1.2 specification. • Two VT-d DMA remap engines.
Technologies 3.2 Intel® Trusted Execution Technology (Intel® TXT) Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision.
Technologies 3.4 Intel® Turbo Boost Technology Intel® Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency/render clock if it is operating below power, temperature, and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. Maximum frequency is dependant on the SKU and number of active cores.
Technologies 3.5 Intel® Advanced Vector Extensions (Intel® AVX) Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128bit vectors into 256-bit vectors.
Technologies • Provides extensions to scale processor addressability for both the logical and physical destination modes • Adds new features to enhance performance of interrupt delivery • Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following: • Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations — In xAPIC compatibil
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Power Management 4 Power Management This chapter provides information on the following power management topics: • • • • • • Figure 4-1.
Power Management 4.1 Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State G0/S0 G1/S3-Cold Description Full On Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot. G3 Mechanical off.
Power Management 4.1.5 Direct Media Interface (DMI) States Table 4-5. Direct Media Interface (DMI) States State Description L0 Full on – Active transfer state L0s First Active Power Management low power state – Low exit latency L1 Lowest Active Power Management – Longer exit latency L3 Lowest power state (power-off) – Longest exit latency 4.1.6 Processor Graphics Controller States Table 4-6.
Power Management 4.2 Processor Core Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies. 4.2.
Power Management Figure 4-2. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 1 Thread 0 Core 0 State Thread 1 Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in Figure 4-3. Figure 4-3.
Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.
Power Management 4.2.4.2 Core C1/C1E State C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.
Power Management 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package Cstates unless specified otherwise: • A package C-state request is determined by the lowest numerical core C-state amongst all cores. • A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components.
Power Management Figure 4-4. Package C-State Entry and Exit C0 C3 C1 4.2.5.1 C6 Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. • The platform has not granted a request to a package C6 state but has allowed a package C6 state. In package C3-state, the L3 shared cache is valid. 4.2.5.
Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations. The CKE is one of the power-save means. When CKE is off the internal DDR clock is disabled and the DDR power is reduced.
Power Management Selection of power modes should be according to power-performance or thermal tradeoffs of a given system: • When trying to achieve maximum performance and power or thermal consideration is not an issue: use no power-down. • In a system that tries to minimize power-consumption, try to use the deepest power-down mode possible – DLL-off or APD_DLLoff.
Power Management 4.3.2.3 Dynamic Power-down Operation Dynamic power-down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down. The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power-down state. The processor core controller can be configured to put the devices in active powerdown (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion with all pages closed).
Power Management 4.6 Graphics Power Management 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR) The Intel Rapid Memory Power Management puts rows of memory into self refresh mode during C3/C6 to allow the system to remain in the lower power states longer. Desktop processors routinely save power during runtime conditions by entering the C3, C6 state. Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole. 4.6.
Power Management 4.6.5 Intel® Graphics Dynamic Frequency Intel® Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and/or voltage above the ensured processor and graphics frequency for the given part. Intel® Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance.
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Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the 2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop, and LGA1155 Socket Thermal and Mechanical Specifications and Design Guidelines.
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Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal (see Table 6-1). Table 6-1.
Signal Description 6.1 System Memory Interface Signals Table 6-2. Memory Channel A Signals Signal Name Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_WE# Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.
Signal Description Table 6-3. Memory Channel B Signals Signal Name Description Direction/ Buffer Type Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_WE# Write Enable Control Signal: This signal is used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_RAS# RAS Control Signal: This signal is used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.
Signal Description 6.3 Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals Signal Name Direction/ Buffer Type Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane.
Signal Description 6.4 PCI Express*-Based Interface Signals Table 6-6.
Signal Description 6.6 Direct Media Interface (DMI) Signals Table 6-8. Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface Signal Name DMI_RX[3:0] DMI_RX#[3:0] DMI Input from PCH: Direct Media Interface receive differential pair. I DMI DMI_TX[3:0] DMI_TX#[3:0] DMI Output to PCH: Direct Media Interface transmit differential pair. O DMI 6.7 Phase Lock Loop (PLL) Signals Table 6-9. Phase Lock Loop (PLL) Signals Signal Name BCLK BCLK# 6.
Signal Description 6.9 Error and Thermal Protection Signals Table 6-11. Error and Thermal Protection Signals 6.10 Signal Name Description Direction/ Buffer Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.
Signal Description 6.11 Processor Power Signals Table 6-13. Processor Power Signals Signal Name VCC Processor core power rail Ref VCCIO Processor power for I/O Ref VDDQ Processor I/O supply voltage for DDR3 Ref VCCAXG Graphics core power supply. Ref VCCPLL VCCPLL provides isolated power for internal processor PLLs Ref System Agent power supply Ref VCCSA 6.
Signal Description 6.14 Processor Internal Pull-Up / Pull-Down Resistors Table 6-16.
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Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Lands The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core operating frequency, memory controller frequency, system agent frequencies, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by the BCLK frequency.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 0 0 0 0 0 0 0 0 0 0.00000 1 0 0 0 0 0 0 0 8 0 0.88500 0 0 0 0 0 0 0 1 0 1 0.25000 1 0 0 0 0 0 0 1 8 1 0.89000 0 0 0 0 0 0 1 0 0 2 0.25500 1 0 0 0 0 0 1 0 8 2 0.89500 0 0 0 0 0 0 1 1 0 3 0.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 2 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX B 0.46000 1 0 1 0 1 0 1 HEX VCC_MAX 1 A B 1.10000 1.10500 0 0 1 0 1 0 1 1 2 0 0 1 0 1 1 0 0 2 C 0.46500 1 0 1 0 1 1 0 0 A C 0 0 1 0 1 1 0 1 2 D 0.47000 1 0 1 0 1 1 0 1 A D 1.11000 0 0 1 0 1 1 1 0 2 E 0.
Electrical Specifications Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3) VID VID VID VID 7 6 5 4 VID VID VID 3 2 1 VID 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 1 0 1 0 1 1 0 5 6 0.67500 1 1 0 1 0 1 1 0 D 6 1.31500 0 1 0 1 0 1 1 1 5 7 0.68000 1 1 0 1 0 1 1 1 D 7 1.32000 0 1 0 1 1 0 0 0 5 8 0.68500 1 1 0 1 1 0 0 0 D 8 1.32500 0 1 0 1 1 0 0 1 5 9 0.
Electrical Specifications 7.5 System Agent (SA) VCC VID The VCCSA is configured by the processor output pin VCCSA_VID. VCCSA_VID output default logic state is low for the processors; logic high is reserved for future compatibility. Table 7-2 specifies the different VCCSA_VID configurations. Table 7-2.
Electrical Specifications 7.7 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications 7.9 Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity that the device is exposed to while being stored in a moisture barrier bag. The specified storage conditions are for component level prior to board attach. Table 7-4 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur.
Electrical Specifications 7.10 DC Specifications The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 8 for the processor land listings and Chapter 6 for signal definitions. Voltage and current specifications are detailed in Table 7-5, Table 7-6, and Table 7-7. The DC specifications for the DDR3 signals are listed in Table 7-8 Control Sideband and Test Access Port (TAP) are listed in Table 7-9.
Electrical Specifications Table 7-5.
Electrical Specifications Table 7-6. Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 1 2 VCCSA Voltage for the system agent 0.879 0.925 0.971 V VDDQ Processor I/O supply voltage for DDR3 1.425 1.5 1.575 V 1.71 1.8 1.89 V -2/-3% 1.05 +2/+3% V Current for the system agent — — 8.8 A ISA_TDC Sustained current for the system agent — — 8.2 A IDDQ Processor I/O supply current for DDR3 — — 4.
Electrical Specifications Table 7-7. Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications Symbol VAXG GFX_VID Range LLAXG VAXGTOB VAXGRipple Parameter GFX_VID Range for VCCAXG Min Typ Max Unit Note2 0.2500 — 1.5200 V 1 4.1 mΩ 3, 4 19 11.
Electrical Specifications Table 7-8. Symbol DDR3 Signal Group DC Specifications Parameter Min Typ Max Units Notes1,9 — SM_VREF – 0.1 V 2,4 V 3 VIL Input Low Voltage — VIH Input High Voltage SM_VREF + 0.1 — — — (VDDQ / 2)* (RON /(RON+RTERM)) — — VDDQ – ((VDDQ / 2)* (RON/(RON+RTERM)) — V 4,6 VOL VOH Output Low Voltage Output High Voltage 6 RON_UP(DQ) DDR3 data buffer pull-up resistance 24.31 28.6 32.9 Ω 5 RON_DN(DQ) DDR3 data buffer pull-down resistance 22.88 28.
Electrical Specifications Table 7-9. Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes1 VCCIO * 0.3 V 2 VIL Input Low Voltage — VIH Input High Voltage VCCIO * 0.7 — V 2, 4 VOL Output Low Voltage — VCCIO * 0.1 V 2 VOH Output High Voltage VCCIO * 0.9 — V 2, 4 RON Buffer on Resistance 23 73 Ω Input Leakage Current — ±200 μA ILI 3 Notes: 1.
Electrical Specifications 7.11 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 7.11.2 DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO. The set of DC electrical specifications shown in Table 7-11 is used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system. For specific nominal VCCIO levels, refer to Table 7-6. Table 7-11.
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Processor Pin and Signal Information 8 Processor Pin and Signal Information 8.1 Processor Pin Assignments The processor pinmap quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-1 provides a listing of all processor pins ordered alphabetically by pin name.
Processor Pin and Signal Information Figure 8-1.
Processor Pin and Signal Information Figure 8-2.
Processor Pin and Signal Information Figure 8-3.
Processor Pin and Signal Information Figure 8-4.
Processor Pin and Signal Information Table 8-1. Pin Name 94 Processor Pin List by Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Pin # Buffer Type Dir. Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Pin # Buffer Type Dir. SA_DQ[26] AV9 DDR3 I/O SA_DQS[6] Pin Name SA_DQ[27] AU9 DDR3 I/O SA_DQ[28] AV7 DDR3 I/O SA_DQ[29] AW7 DDR3 I/O SA_DQ[30] AW9 DDR3 Processor Pin List by Pin Name Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Processor Pin List by Pin Name Pin Name Table 8-1. Processor Pin List by Pin Name Pin # Buffer Type Dir. Pin # Buffer Type Dir.
Processor Pin and Signal Information Table 8-1. Pin Name 100 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name VCC Processor Pin List by Pin Name Dir. Table 8-1.
Processor Pin and Signal Information Table 8-1. Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1.
Processor Pin and Signal Information Table 8-1. Pin Name 104 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name 106 Processor Pin List by Pin Name Table 8-1. Dir.
Processor Pin and Signal Information Table 8-1. Pin Name Processor Pin List by Pin Name Pin # Buffer Type VSS V5 GND VSS W6 GND VSS Y5 GND VSS Y8 GND VSS_NCTF A4 GND VSS_NCTF AV39 GND VSS_NCTF AY37 GND VSS_NCTF Dir.
Processor Pin and Signal Information 108 Datasheet, Volume 1
DDR Data Swizzling 9 DDR Data Swizzling To achieve better memory performance and better memory timing, Intel design performed the DDR Data pin swizzling that will allow a better use of the product across different platforms. Swizzling has no effect on functional operation and is invisible to the OS/SW. However, during debug, swizzling needs to be taken into consideration. This chapter presents swizzling data.
DDR Data Swizzling Table 9-1. Pin Name 110 DDR Data Swizzling Table – Channel A Pin # MC Pin Name SA_DQ[0] AJ3 DQ01 SA_DQ[1] AJ4 DQ02 SA_DQ[2] AL3 SA_DQ[3] AL4 SA_DQ[4] SA_DQ[5] Table 9-1.
DDR Data Swizzling Table 9-2. Pin Name DDR Data Swizzling Table – Channel B Table 9-2.
DDR Data Swizzling 112 Datasheet, Volume 1
