2nd Generation Intel® Core™ Processor Family Mobile and Intel® Celeron® Processor Family Mobile Datasheet, Volume 1 Supporting Intel® Core™ i7 Mobile Extreme Edition Processor Series and Intel® Core™ i5 and i7 Mobile Processor Series Supporting Intel® Celeron® Mobile Processor Series This is Volume 1 of 2 September 2012 Document Number: 324692-006
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Contents 1 Introduction ............................................................................................................ 11 1.1 Processor Feature Details ................................................................................... 13 1.1.1 Supported Technologies .......................................................................... 13 1.2 Interfaces ........................................................................................................ 13 1.2.
2.4.1 3D and Video Engines for Graphics Processing ........................................... 2.4.1.1 3D Engine Execution Units ......................................................... 2.4.1.2 3D Pipeline .............................................................................. 2.4.1.3 Video Engine ........................................................................... 2.4.1.4 2D Engine ............................................................................... 2.4.
4.3 4.4 4.5 4.6 4.7 4.2.4.4 Core C6 State........................................................................... 49 4.2.4.5 Core C7 State........................................................................... 49 4.2.4.6 C-State Auto-Demotion.............................................................. 50 4.2.5 Package C-States ................................................................................... 50 4.2.5.1 Package C0 .................................................................
.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 Embedded DisplayPort* (eDP) Signals ................................................................. Intel® Flexible Display Interface (Intel® FDI) Signals............................................. Direct Media Interface (DMI) Signals ................................................................... Phase Lock Loop (PLL) Signals ............................................................................ Test Access Points (TAP) Signals .........
Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 4-1 4-2 4-3 4-4 5-1 5-2 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 Mobile Platform System Block Diagram Example ......................................................... 12 Intel® Flex Memory Technology Operation.................................................................. 23 PCI Express* Layering Diagram ................................................................................
4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 8-1 8-2 8-3 9-1 9-2 8 Processor Graphics Controller States ........................................................................ 45 G, S, and C State Combinations............................................................................... 45 D, S, and C State Combination ......................................
Revision History Revision Number 001 Description • Initial Release Date January 2011 Intel® 002 • Added Core™ i7-2677M, i7-2637M, and i5-2557M processors • Added Intel® Celeron® B800 and 847 processors June 2011 003 • Added Intel® Celeron® 787 and 857 processors July 2011 Intel® Celeron® 004 • Added 005 • Added Intel® Core™ i7-2960XM, i7-2860QM, i7-2760QM, and i7-2640M processors • Added Intel® Celeron® B840 processor B710 processor July 2011 September 2011 006 • Added Intel® Celeron® B83
Datasheet, Volume 1
Introduction 1 Introduction The 2nd Generation Intel® Core™ processor family mobile and Intel® Celeron® processor family mobile are the next generation of 64-bit, multi-core mobile processor built on 32- nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform. The two-chip platform consists of a processor and Platform Controller Hub (PCH). The platform enables higher performance, lower cost, easier validation, and improved x-y footprint.
Introduction Figure 1-1.
Introduction 1.1 Processor Feature Details • Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores 1.1.
Introduction • Memory organizations — Single-channel modes — Dual-channel modes - Intel® Flex Memory Technology: - Dual-channel symmetric (Interleaved) • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT • Intel® Fast Memory Access (Intel® FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.2.2 PCI Express* • PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0.
Introduction • Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering) • Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0 — DMI -> PCI Express* Port 0 — DMI -> PCI Express* Port 1 — PCI Express* Port 0 -> DMI — PCI Express* Port 1 -> DMI • 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream
Introduction • Supports the following traffic types to or from the PCH — DMI -> DRAM — DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only) — Processor core -> DMI • APIC and MSI interrupt messaging support — Message Signaled Interrupt (MSI and MSI-X) messages • Downstream SMI, SCI and SERR error indication • Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters • DC coupling – no capacitors between the processor and
Introduction 1.2.6 Embedded DisplayPort* (eDP) • Stand alone dedicated port (unlike previous generation processor that shared pins with PCIe interface) 1.2.
Introduction 1.3.6 Processor Graphics Controller • Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR • Intel® Graphics Performance Modulation Technology (Intel® GPMT) • Intel Smart 2D Display Technology (Intel S2DDT) • Graphics Render C-State (RC6) • Intel Seamless Display Refresh Rate Switching with Embedded DisplayPort* 1.
Introduction Table 1-2. Terminology (Sheet 2 of 3) Term Description Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system.
Introduction Table 1-2. Terminology (Sheet 3 of 3) Term 1.7 Description VCC Processor core power supply. VCCIO High Frequency I/O logic power supply VCCPLL PLL power supply VCCSA System Agent (memory controller, DMI, PCIe controllers, and display engine) power supply VDDQ DDR3 power supply. VLD Variable Length Decoding. VSS Processor ground. x1 Refers to a Link or Port with one Physical Lane. x16 Refers to a Link or Port with sixteen Physical Lanes.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one DIMM. It supports a maximum of one unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing up to two device ranks per-channel.
Interfaces 2.1.2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: • tCL = CAS Latency • tRCD = Activate Command to READ or WRITE Command delay • tRP = PRECHARGE Command Period • CWL = CAS Write Latency • Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks.
Interfaces Figure 2-1. Intel® Flex Memory Technology Operation 2.1.3.2.1 Dual-Channel Symmetric Mode Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned.
Interfaces 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device. The primary PCI Express Graphics port is referred to as PEG 0. 2.2.
Interfaces through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-3. Packet Flow through the Layers 2.2.1.
Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-4. PCI Express* Related Register Structures in the Processor PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification.
Interfaces 2.2.4 PCI Express* Lanes Connection Figure 2-5 demonstrates the PCIe lanes mapping. Figure 2-5. PCI Express* Typical Operation 16 lanes Mapping 2.3 Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI2 is supported. Note: Only DMI x4 configuration is supported. 2.3.1 DMI Error Flow DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0.
Interfaces 2.3.3 DMI Link Down The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH. Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal.
Interfaces 2.4.1 3D and Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the following performance and power-management enhancements: • Up to 12 Execution units (EUs) • Hierarchal-Z • Video quality enhancements 2.4.1.1 3D Engine Execution Units • Supports up to 12 EUs.
Interfaces 2.4.1.2.6 Windower/IZ (WIZ) Stage The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead. The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible.
Interfaces 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • Embedded DisplayPort* and Intel® FDI Figure 2-7. Processor Display Block Diagram 2.4.2.1 Display Planes A display plane is a single displayed surface in memory and contains one image (desktop, cursor, overlay).
Interfaces 2.4.2.1.3 Cursors A and B Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each. 2.4.2.1.4 Video Graphics Array (VGA) VGA is used for boot, safe mode, legacy games, etc. It can be changed by an application without OS/driver notification, due to legacy requirements. 2.4.2.
Interfaces 2.4.4 Multi-Graphics Controller Multi-Monitor Support The processor supports simultaneous use of the Processor Graphics Controller (GT) and a x16 PCI Express Graphics (PEG) device. The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH. Note: When supporting Multi Graphics controllers Multi-Monitors, “drag and drop” between monitors and the 2x8 PEG is not supported. 2.
Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
Technologies 3.1.
Technologies 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features The processor supports the following Intel VT-d features: • Memory controller and Processor Graphics comply with Intel® VT-d 1.2 specification. • Two VT-d DMA remap engines.
Technologies 3.2 Intel® Trusted Execution Technology (Intel® TXT) Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision.
Technologies 3.4 Intel® Turbo Boost Technology Compared with previous generation products, Intel Turbo Boost Technology will increase the ratio of application power to TDP. Thus, thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time. Note: Intel Turbo Boost Technology may not be available on all SKUs.
Technologies 3.4.2 Intel® Turbo Boost Technology Graphics Frequency The graphics render frequency is selected dynamically based on graphics workload demand as permitted by the processor turbo control. The processor can optimize both processor and Processor Graphics performance through power sharing. The processor cores and the processor graphics core share a package power limit.
Technologies 3.6.1 PCLMULQDQ Instruction The processor supports the carry-less multiplication instruction, PCLMULQDQ. PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the 128-bit carry-less multiplication of two, 64-bit operands without generating and propagating carries. Carry-less multiplication is an essential processing component of several cryptographic systems and standards.
Technologies • More efficient MSR interface to access APIC registers — To enhance inter-processor and self directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in the x2APIC mode.
Power Management 4 Power Management This chapter provides information on the following power management topics: • • • • • • Figure 4-1.
Power Management 4.1 Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State G0/S0 G1/S3-Cold Description Full On Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH). G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot. G3 Mechanical off.
Power Management 4.1.4 PCI Express* Link States Table 4-4. PCI Express* Link States State Description L0 Full on – Active transfer state L0s First Active Power Management low power state – Low exit latency L1 Lowest Active Power Management – Longer exit latency L3 Lowest power state (power-off) – Longest exit latency 4.1.5 Direct Media Interface (DMI) States Table 4-5.
Power Management Table 4-8. D, S, and C State Combination Graphics Adapter (D) State 4.
Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel HT Technology is enabled.
Power Management Table 4-9. Coordination of Thread Power States at the Core Level Processor Core C-State C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C1 C0 C11 C1 C3 C0 C11 C3 C3 C3 C0 C11 C3 C6 C6 C0 C11 C3 C6 C7 C0 Thread 0 C6 C7 Note: 4.2.3 Thread 1 1 C1 1 C11 If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.
Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: • A core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-7.
Power Management 4.2.4.6 C-State Auto-Demotion In general, deeper C-states such as C6 or C7 have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on battery life idle. To increase residency and improve battery life idle in deeper C-states, the processor supports C-state auto-demotion.
Power Management Table 4-11. Coordination of Core Power States at the Package Level Core 1 Package C-State Core 0 Note: C0 C1 C3 C6 C7 C0 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C11 C3 C0 C11 C3 C3 C3 C6 C0 C11 C3 C6 C6 C7 C0 C11 C3 C6 C7 If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher. Figure 4-4. Package C-State Entry and Exit 4.2.5.1 Package C0 This is the normal operating state for the processor.
Power Management 4.2.5.2 Package C1/C1E No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. The package enters the C1 low power state when: • At least one core is in the C1 state. • The other cores are in a C1 or lower power state.
Power Management 4.2.5.5 Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state and the L3 cache is completely flushed. The last core to enter the C7 state begins to shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows further power savings. Core break events are handled the same way as in package C3 or C6.
Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals that the SDRAM controller supports. The processor drives four CKE pins to perform these operations. The CKE is one of the power-save means. When CKE is off the internal DDR clock is disabled and the DDR power is reduced.
Power Management Selection of power modes should be according to power-performance or thermal tradeoffs of a given system: • When trying to achieve maximum performance and power or thermal consideration is not an issue: use no power-down. • In a system that tries to minimize power-consumption, try to use the deepest power-down mode possible – DLL-off or APD_DLLoff.
Power Management Table 4-12. Targeted Memory State Conditions Mode Memory State with Processor Graphics Memory State with External Graphics C0, C1, C1E Dynamic memory rank power down based on idle conditions. Dynamic memory rank power down based on idle conditions. If the Processor Graphics engine is idle and there are no pending display requests, then enter self-refresh. Otherwise, use dynamic memory rank power down based on idle conditions. If there are no memory requests, then enter self-refresh.
Power Management 4.6 Graphics Power Management 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR) The Intel Rapid Memory Power Management puts rows of memory into self refresh mode during C3/C6/C7 to allow the system to remain in the lower power states longer. Mobile processors routinely save power during runtime conditions by entering the C3, C6, or C7 state. Intel RMPM is an indirect method of power saving that can have a significant effect on the system as a whole. 4.6.
Power Management 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT) Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh. Power consumption is reduced by less accesses to the IMC. S2DDT is only enabled in single pipe mode. Intel S2DDT is most effective with: • Display images well suited to compression, such as text windows, slide shows, and so on. Poor examples are 3D games.
Power Management 4.6.7 Automatic Display Brightness (ADB) This is a mobile only supported power management feature. Intel® Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment. This feature requires an additional sensor to be on the panel front. The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver.
Power Management 60 Datasheet, Volume 1
Thermal Management 5 Thermal Management The thermal solution provides both the component-level and the system-level thermal management. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor: • Remains below the maximum junction temperature (Tj,Max) specification at the maximum thermal design power (TDP).
Thermal Management 5.2.1 Intel® Turbo Boost Technology Power Control and Reporting When operating in the turbo mode, the processor will monitor its own power and adjust the turbo frequency to maintain the average power within limits over a thermally significant time period. The package, processor core, and graphic core powers are estimated using architectural counters and do not rely on any input from the platform.
Thermal Management 5.2.2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations. Figure 5-1. Package Power Control 5.2.3 Power Plane Control The processor core and graphics core power plane controls allow for customization to implement optimal turbo within voltage regulator thermal limitations.
Thermal Management 5.3 Thermal and Power Specifications The following notes apply to Table 5-1, Table 5-2, Table 5-3, and Table 5-4. 64 Notes Description 1 The TDPs given are not the maximum power the processor can generate. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time. 2 TDP workload may consist of a combination of a CPU-core intensive and a graphics-core intensive applications.
Thermal Management Table 5-1. Thermal Design Power (TDP) Specifications Segment State CPU Core Frequency Processor Graphics Core frequency Thermal Design Power HFM 2.5 GHz up to 3.5 GHz 650 MHz up to 1300 MHz 55 LFM 800 MHz 650 MHz up to 1300 MHz 36 HFM 2.2 GHz up to 3.4 GHz 650 MHz up to 1300 MHz 45 LFM 800 MHz 650 MHz up to 1300 MHz 33 HFM 2.5 GHz up to 3.4 GHz 650 MHz up to 1300 MHz 35 LFM 800 MHz 650 MHz up to 1300 MHz 26 HFM 2.1 GHz up to 3.
Thermal Management Table 5-3. Package Turbo Parameters (Sheet 2 of 2) Segment Quad Core SV Dual Core SV Low Voltage Ultra Low Voltage 66 Symbol Package Turbo Parameter Min H/W Default Max Units Notes Turbo Time Parameter (package) Processor turbo long duration time window (POWER_LIMIT_1_TIME in TURBO_POWER_LIMIT MSR 0610h bits [23:17]) 0.
Thermal Management Table 5-4. Idle Power Specifications Segment Extreme Edition (XE) Quad Core SV Dual Core SV Low Voltage Ultra Low Voltage 5.4 Symbol Idle Parameter Min Typ Max Units Notes PC1E Idle power in the Package C1e state — — 12.5 W 6, 8 PC6 Idle power in the Package C6 state — — 4 W 6, 9 PC7 Idle power in the Package C7state — — 3.85 W 6, 9 PC1E Idle power in the Package C1e state — — 11 W 6, 8 PC6 Idle power in the Package C6 state — — 3.
Thermal Management The Adaptive Thermal Monitor can be activated when any package temperature, monitored by a digital thermal sensor (DTS), meets or exceeds its maximum junction temperature specification (TJ,max) and asserts PROCHOT#. The thermal control circuit (TCC) can be activated prior to TJ,max by use of the TCC activation offset. The assertion of PROCHOT# activates the thermal control circuit (TCC), and causes both the processor core and graphics core to reduce frequency and voltage adaptively.
Thermal Management Figure 5-2. Frequency and Voltage Ordering Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically. • On an upward operating point transition, the voltage transition precedes the frequency transition. • On a downward transition, the frequency transition precedes the voltage transition. When transitioning to a target core operating voltage, a new VID code to the voltage regulator is issued.
Thermal Management 5.4.1.1.2 Clock Modulation If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will use clock modulation. Clock modulation is done by alternately turning the clocks off and on at a duty cycle (ratio between clock “on” time and total time) specific to the processor. The duty cycle is factory configured to 25% on and 75% off and cannot be modified.
Thermal Management The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point. When a package DTS indicates that it has reached the TCC activation (a reading of 0h, except when the TCC activation offset is changed), the TCC will activate and indicate a Adaptive Thermal Monitor event. A TCC activation will lower both IA core and graphics core frequency, voltage or both.
Thermal Management 5.4.1.3.2 Voltage Regulator Protection PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption.
Thermal Management enabled. For more details on the interrupt mechanism, refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals. 5.4.2 Processor Core Specific Thermal Features 5.4.2.1 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption using clock modulation. This mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal Monitor and bi-directional PROCHOT#.
Thermal Management 5.4.4 Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control.
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type. Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal (see Table 6-1). Table 6-1.
Signal Description 6.1 System Memory Interface Signals Table 6-2. Memory Channel A Signals Signal Name Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SA_WE# Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands. O DDR3 SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.
Signal Description Table 6-3. Memory Channel B Signals Signal Name Description Direction/ Buffer Type Bank Select: These signals define which banks are selected within each SDRAM rank. O DDR3 SB_WE# Write Enable Control Signal: This signal is used with SB_RAS# and SB_CAS# (along with SB_CS#) to define the SDRAM Commands. O DDR3 SB_RAS# RAS Control Signal: This signal is used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.
Signal Description 6.3 Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals Signal Name Direction/ Buffer Type Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane. A test point may be placed on the board for this lane.
Signal Description 6.4 PCI Express*-Based Interface Signals Table 6-6. PCI Express* Graphics Interface Signals Signal Name PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO Direction/ Buffer Type Description PCI Express Input Current Compensation I A PCI Express Current Compensation I A PCI Express Resistance Compensation I A PEG_RX[15:0] PEG_RX#[15:0] PCI Express Receive Differential Pair I PCI Express PEG_TX[15:0] PEG_TX#[15:0] PCI Express Transmit Differential Pair O PCI Express 6.
Signal Description 6.6 Intel® Flexible Display Interface (Intel® FDI) Signals Table 6-8.
Signal Description 6.9 Test Access Points (TAP) Signals Table 6-11. Test Access Points (TAP) Signals Signal Name Description Direction/ Buffer Type BPM#[7:0] Breakpoint and Performance Monitor Signals: These signals are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. I/O CMOS BCLK_ITP BCLK_ITP# These pins are connected in parallel to the top side debug probe to enable debug capacities.
Signal Description Table 6-12. Error and Thermal Protection Signals (Sheet 2 of 2) 6.11 Signal Name Description Direction/ Buffer Type THERMTRIP# Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 130 °C.
Signal Description Table 6-14. Processor Power Signals (Sheet 2 of 2) Signal Name 6.13 Description Direction/ Buffer Type VCCDQ (BGA Only) Filtered, low noise derivative of VDDQ VIDSOUT VIDSCLK VIDALERT# VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial synchronous interface used to transfer power management information between the processor and the voltage regulator controllers. This serial VID interface replaces the parallel VID interface on previous processors.
Signal Description 6.15 Future Compatibility Signals Table 6-17. Future Compatibility Signals Signal Name PROC_SELECT# This pin is for compatibility with future platforms. A pull-up resistor to VCPLL is required if connected to the DF_TVS strap on the PCH. SA_DIMM_VREFDQ SB_DIMM_VREFDQ Memory Channel A/B DIMM DQ Voltage Reference: These signals are not used by the processors and are for future compatibility only. No connection is required. VCCIO_SEL VCCSA_VID[0] 6.
Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Pins The processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA, VAXG and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3 Voltage Identification (VID) The VID specifications for the processor VCC and VAXG are defined by the VR12/IMVP7 SVID Protocol. The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages. Table 7-1 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level.
Electrical Specifications Table 7-1. h IMVP7 Voltage Identification Definition (Sheet 1 of 3) VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 0 0 0 0 0 0 0 0 0 0.00000 1 0 0 0 0 0 0 0 8 0 0.88500 0 0 0 0 0 0 0 1 0 1 0.25000 1 0 0 0 0 0 0 1 8 1 0.89000 0 0 0 0 0 0 1 0 0 2 0.25500 1 0 0 0 0 0 1 0 8 2 0.89500 0 0 0 0 0 0 1 1 0 3 0.
Electrical Specifications Table 7-1. IMVP7 Voltage Identification Definition (Sheet 2 of 3) VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 0 1 0 1 0 1 1 2 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX B 0.46000 1 0 1 0 1 0 1 1 A 2 C 0.46500 1 0 1 0 1 1 0 0 2 D 0.
Electrical Specifications Table 7-1. IMVP7 Voltage Identification Definition (Sheet 3 of 3) VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 HEX VCC_MAX 0 1 0 1 0 1 1 0 5 6 0.67500 1 1 0 1 0 1 1 0 D 6 1.31500 0 1 0 1 0 1 1 1 5 7 0.68000 1 1 0 1 0 1 1 1 D 7 1.32000 0 1 0 1 1 0 0 0 5 8 0.68500 1 1 0 1 1 0 0 0 D 8 1.32500 0 1 0 1 1 0 0 1 5 9 0.
Electrical Specifications 7.4 System Agent (SA) VCC VID The VccSA is configured by the processor output pins VCCSA_VID[1:0]. VCCSA_VID[0] output default logic state is low for the 2nd Generation Intel® Core™ processor family mobile and Intel® Celeron® processor family mobile. Logic high is reserved for future compatibility. VCCSA_VID[1] output default logic state is low – will not change the SA voltage. Logic high will reduce the voltage. Note: During boot, the processor’s VccSA is 0.9 V.
Electrical Specifications 7.6 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals, have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 7-3.
Electrical Specifications Table 7-3.
Electrical Specifications Table 7-3. Signal Groups1 (Sheet 3 of 3) Signal Group ® Intel Type Signals FDI Single Ended CMOS Input FDI0_FSYNC, FDI1_FSYNC, FDI0_LSYNC, FDI1_LSYNC Single Ended Asynchronous CMOS Input FDI_INT Differential FDI Output FDI0_TX[3:0], FDI0_TX#[3:0], FDI1_TX[3:0], FDI1_TX#[3:0] Future Compatibility PROC_SELECT#, VCCSA_VID[0], VCCIO_SEL, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ Notes: 1. Refer to Chapter 6 for signal description details. 2.
Electrical Specifications Table 7-4. Storage Condition Ratings Symbol Parameter Min Max Notes -25 °C 125 °C 1, 2, 3, 4 5, 6 Tabsolute storage The non-operating device storage temperature. Damage (latent or otherwise) may occur when exceeded for any length of time. Tsustained storage The ambient storage temperature (in shipping media) for a sustained period of time -5 °C 40 °C Tshort term storage The ambient storage temperature (in shipping media) for a short period of time.
Electrical Specifications 7.9.1 Voltage and Current Specifications Table 7-5. Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications (Sheet 1 of 2) Symbol Parameter HFM_VID VID Range for Highest Frequency Mode (Includes Turbo Mode Operation) XE SV-QC SV-DC LV ULV 0.8 0.8 0.8 0.75 0.7 LFM_VID VID Range for Lowest Frequency Mode XE SV-QC SV-DC LV ULV 0.65 0.65 0.65 0.65 0.
Electrical Specifications Table 7-5. Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications (Sheet 2 of 2) Symbol SLOPELL Parameter Processor Loadline Segment XE SV-QC SV-DC LV ULV Min Typ Max Unit — -1.9 -1.9 -1.9 -2.9 -2.9 — mΩ Note Notes: 1. Unless otherwise noted, all specifications in this table are based on post-silicon estimates and simulations or empirical data. 2.
Electrical Specifications Table 7-7. Memory Controller (VDDQ) Supply DC Voltage and Current Specifications Symbol VDDQ(DC+AC) TOLDDQ Parameter Processor I/O supply voltage for DDR3 (DC + AC specification) Min Typ Max Unit — 1.5 — V VDDQ Tolerance DC= ±3% AC= ±2% AC+DC= ±5% % ICCMAX_VDDQ Max Current for VDDQ Rail — — 5 A ICCAVG_VDDQ Average Current for VDDQ Rail during Standby — 66 133 mA (Standby) Note 1 Notes: 1.
Electrical Specifications Table 7-10. Processor Graphics (VAXG) Supply DC Voltage and Current Specifications Symbol GFX_VID VAXG Parameter Active VID Range for VAXG XE, SV-QC, SV-DC LV ULV Min 0.65 0.65 0.65 Processor Graphics core voltage Typ — Max 1.35 1.35 1.35 0 – 1.
Electrical Specifications Table 7-11. DDR3 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage — — SM_VREF -0.1 V 2, 4, 11 VIH Input High Voltage SM_VREF + 0.1 — — V 3, 11 VIL Input Low Voltage (SM_DRAMPWROK) — — VDDQ*0.55 -0.1 V 10 VIH Input High Voltage (SM_DRAMPWROK) VDDQ*0.55 +0.
Electrical Specifications Table 7-12. Control Sideband and TAP Signal Group DC Specifications Symbol Parameter Min Max Units Notes1 VCCIO * 0.3 V 2 VIL Input Low Voltage — VIH Input High Voltage VCCIO * 0.7 — V 2, 4 VOL Output Low Voltage — VCCIO * 0.1 V 2 VOH Output High Voltage VCCIO * 0.9 — V 2, 4 RON Buffer on Resistance 23 73 Input Leakage Current — ±200 A ILI 3 Notes: 1.
Electrical Specifications Table 7-14. Embedded DisplayPort* DC Specifications Symbol Parameter Min Typ Max Units Notes eDP_HPD# VIL Input Low Voltage -0.1 — 0.3 * VCCIO V VIH Input High Voltage 0.7 * VCCIO — VCCIO V eDP_AUX, eDP_AUX# VAUX-DIFFp-p (Tx) AUX Peak-to-Peak Voltage at the transmitting device 0.4 — 0.6 1 VAUX-DIFFp-p (Rx) AUX Peak-to-Peak Voltage at the receiving device 0.32 — 1.36 V 1 eDP COMPs eDP_ICOMPI Comp Resistance 24.75 25 25.
Electrical Specifications Figure 7-1. Example for PECI Host-clients Connection 7.10.2 PECI DC Characteristics The PECI interface operates at a nominal voltage set by VCCIO The set of DC electrical specifications shown in Table 7-15 are used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system.
Electrical Specifications 7.10.3 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design. Figure 7-2.
Electrical Specifications 104 Datasheet, Volume 1
Processor Pin and Signal Information 8 Processor Pin and Signal Information 8.1 Processor Pin Assignments • Table 8-1, Table 8-2 and Table 8-3 all pins ordered alphabetically for the rPGA988B BGA1224 and BGA1023 package respectively. • Figure 8-1, Figure 8-2, Figure 8-3 and Figure 8-4 show the Top-Down view of the rPGA988B pinmap. • Figure 8-5, Figure 8-6, Figure 8-7 and Figure 8-8 show the Top-Down view of the BGA1224 ballmap.
Processor Pin and Signal Information Figure 8-1.
Processor Pin and Signal Information Figure 8-2.
Processor Pin and Signal Information Figure 8-3.
Processor Pin and Signal Information Figure 8-4.
Processor Pin and Signal Information Table 8-1. Pin Name 110 rPGA988B Processor Pin List by Pin Name Pin # Buffer Type Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. Datasheet, Volume 1 rPGA988B Processor Pin List by Pin Name Table 8-1.
Processor Pin and Signal Information Table 8-1. 112 rPGA988B Processor Pin List by Pin Name Pin Name Pin # RSVD AK32 RSVD AK2 RSVD AJ32 RSVD Buffer Type Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. Pin Name Datasheet, Volume 1 rPGA988B Processor Pin List by Pin Name Pin # Buffer Type Table 8-1.
Processor Pin and Signal Information Table 8-1. 114 rPGA988B Processor Pin List by Pin Name Pin Name Pin # SB_DQ[24] M5 SB_DQ[25] N4 SB_DQ[26] N2 SB_DQ[27] N1 SB_DQ[28] Buffer Type Table 8-1.
Processor Pin and Signal Information Table 8-1. Datasheet, Volume 1 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VAXG AH23 VAXG AH24 VAXG Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. 116 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VCC AG28 VCC AG29 VCC VCC Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. Datasheet, Volume 1 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VCCIO F13 PWR VCCIO F14 PWR VCCIO G13 VCCIO Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. 118 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VSS AH4 GND VSS AH7 GND VSS AJ1 VSS Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. Datasheet, Volume 1 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VSS B15 VSS B17 VSS Dir Table 8-1.
Processor Pin and Signal Information Table 8-1. 120 rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type VSS N30 VSS N31 VSS VSS Dir Table 8-1.
Processor Pin and Signal Information Figure 8-5.
Processor Pin and Signal Information Figure 8-6.
Processor Pin and Signal Information Figure 8-7.
Processor Pin and Signal Information Figure 8-8.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Datasheet, Volume 1 Ball Name Ball # Buffer Type Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 126 Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Datasheet, Volume 1 Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name 128 Ball # Buffer Type Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Datasheet, Volume 1 Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 130 Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Datasheet, Volume 1 Ball Name Ball # Buffer Type VAXG AF58 VAXG AF56 VAXG Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 132 Ball Name Ball # Buffer Type VCC L40 VCC L38 VCC Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Datasheet, Volume 1 Ball # Buffer Type Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 134 Ball Name Ball # Buffer Type VCCSA N16 VCCSA N14 VCCSA Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Datasheet, Volume 1 Ball Name Ball # Buffer Type VSS BJ48 VSS BJ40 VSS Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 136 Ball Name Ball # Buffer Type VSS AV63 VSS AV59 VSS Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name Datasheet, Volume 1 Ball Name Ball # Buffer Type VSS AF63 VSS AF61 VSS Dir Table 8-2.
Processor Pin and Signal Information Table 8-2. BGA1224 Processor Ball List by Ball Name 138 Ball Name Ball # VSS L12 VSS L8 VSS K39 VSS VSS Buffer Type Dir Table 8-2.
Processor Pin and Signal Information Table 8-2.
Processor Pin and Signal Information Figure 8-9.
Processor Pin and Signal Information Figure 8-10.
Processor Pin and Signal Information Figure 8-11.
Processor Pin and Signal Information Figure 8-12.
Processor Pin and Signal Information Table 8-3. BGA1023 Processor Ball List by Ball Name Ball Name 144 Ball # Buffer Type Table 8-3.
Processor Pin and Signal Information Table 8-3. Ball Name Datasheet, Volume 1 BGA1023 Processor Ball List by Ball Name Table 8-3.
Processor Pin and Signal Information Table 8-3. Ball Name 146 BGA1023 Processor Ball List by Ball Name Ball # Buffer Type Dir Table 8-3.
Processor Pin and Signal Information Table 8-3. Datasheet, Volume 1 BGA1023 Processor Ball List by Ball Name Buffer Type Table 8-3.
Processor Pin and Signal Information Table 8-3. Ball Name 148 BGA1023 Processor Ball List by Ball Name Table 8-3.
Processor Pin and Signal Information Table 8-3.
Processor Pin and Signal Information Table 8-3. 150 BGA1023 Processor Ball List by Ball Name Ball Name Ball # Buffer Type VCC E38 VCC E37 VCC Dir Table 8-3.
Processor Pin and Signal Information Table 8-3. Datasheet, Volume 1 BGA1023 Processor Ball List by Ball Name Ball Name Ball # VCCSA U15 VCCSA R21 VCCSA R18 VCCSA Buffer Type Dir Table 8-3.
Processor Pin and Signal Information Table 8-3. 152 BGA1023 Processor Ball List by Ball Name Ball Name Ball # VSS AW13 VSS AW7 VSS AV55 VSS Buffer Type Dir Table 8-3.
Processor Pin and Signal Information Table 8-3. Datasheet, Volume 1 BGA1023 Processor Ball List by Ball Name Dir Table 8-3.
Processor Pin and Signal Information Table 8-3. 154 BGA1023 Processor Ball List by Ball Name Dir Table 8-3.
Processor Pin and Signal Information 8.2 Package Mechanical Information Figure 8-13.
Processor Pin and Signal Information Figure 8-14.
Processor Pin and Signal Information Figure 8-15.
Processor Pin and Signal Information Figure 8-16.
Processor Pin and Signal Information Figure 8-17.
Processor Pin and Signal Information Figure 8-18.
Processor Pin and Signal Information Figure 8-19.
Processor Pin and Signal Information Figure 8-20.
Processor Pin and Signal Information Figure 8-21.
Processor Pin and Signal Information Figure 8-22.
Processor Pin and Signal Information Figure 8-23.
Processor Pin and Signal Information Figure 8-24.
DDR Data Swizzling 9 DDR Data Swizzling To achieve better memory performance and better memory timing; Intel design performed the DDR Data pin swizzling which will allow a better use of the product across different platforms. Swizzling has no effect on functional operation and is invisible to the OS/SW. However, during debug, swizzling needs to be taken into consideration; thus, swizzling data is presented in this chapter.
DDR Data Swizzling Table 9-1. Table 9-1.
DDR Data Swizzling Table 9-2. Table 9-2.
DDR Data Swizzling 170 Datasheet, Volume 1
