Intel® Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US
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Revision History—Intel® Quark Core Revision History Date Revision September 2013 001 October 2013 Order Number: 329679-001US Description First external release of document.
Intel® Quark Core—Contents Contents 1.0 About 1.1 1.2 1.3 1.4 this Manual .......................................................................................................17 Manual Contents................................................................................................17 Notation Conventions .........................................................................................18 Special Terminology ..................................................................................
Contents—Intel® Quark Core 4.5 4.6 4.7 4.8 4.9 4.4.1.1 Control Register 0 (CR0) ............................................................ 47 4.4.1.2 Control Register 1 (CR1) ............................................................ 51 4.4.1.3 Control Register 2 (CR2) ............................................................ 51 4.4.1.4 Control Register 3 (CR3) ............................................................ 51 4.4.1.5 Control Register 4 (CR4) .........................................
Intel® Quark Core—Contents 6.3.5 6.3.6 6.4 6.5 Call Gates ..............................................................................................87 Task Switching .......................................................................................88 6.3.6.1 Floating-Point Task Switching......................................................89 6.3.7 Initialization and Transition to Protected Mode ............................................89 Paging...............................................
Contents—Intel® Quark Core 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9.0 SMM Overview ................................................................................................ 127 Terminology ................................................................................................... 127 System Management Interrupt Processing .......................................................... 128 8.3.1 System Management Interrupt (SMI#).................................................... 129 8.3.
Intel® Quark Core—Contents 9.3 9.4 9.5 9.6 9.2.8.1 Reset Input (RESET) ................................................................ 154 9.2.8.2 Soft Reset Input (SRESET) ....................................................... 155 9.2.8.3 System Management Interrupt Request Input (SMI#) .................. 155 9.2.8.4 System Management Mode Active Output (SMIACT#) .................. 155 9.2.8.5 Maskable Interrupt Request Input (INTR) ................................... 155 9.2.8.
Contents—Intel® Quark Core 9.6.3 9.6.4 9.6.5 9.6.6 Write-Back Enhanced Intel® Quark SoC X1000 Core Pin States During Stop Grant State ......................................................................................... 176 Clock Control State Diagram .................................................................. 177 9.6.4.1 Normal State.......................................................................... 177 9.6.4.2 Stop Grant State .........................................................
Intel® Quark Core—Contents 10.4 10.3.11.2Shutdown Indication Cycle ....................................................... 221 10.3.11.3Stop Grant Indication Cycle ...................................................... 221 10.3.12Bus Cycle Restart ................................................................................. 222 10.3.13Bus States ........................................................................................... 224 10.3.
Contents—Intel® Quark Core 12.3 12.2.5.3 RDTSC .................................................................................. 264 12.2.5.4 WRMSR ................................................................................. 264 Clock Count Summary ..................................................................................... 265 12.3.1 Instruction Clock Count Assumptions ...................................................... 265 A Signal Descriptions .......................................
Intel® Quark Core—Contents 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Base Architecture Registers .......................................................................................40 Flag Registers ..........................................................................................................
Contents—Intel® Quark Core 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 I/O Instruction Restart............................................................................................ 139 SMM Base Location ................................................................................................ 140 SMRAM Usage ...............................................................
Intel® Quark Core—Contents 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 Snoop Cycle Invalidating a Modified Line ................................................................... 231 Snoop Cycle Overlaying a Line-Fill Cycle .................................................................... 232 Snoop Cycle Overlaying a Non-Burst Cycle................................................................. 233 Snoop to the Line that is Being Replaced .................
Contents—Intel® Quark Core 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Descriptor Types Used for Control Transfer .................................................................. 86 Use of CR3 with PAE Paging....................................................................................... 93 Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE) .........................................
Intel® Quark Core—Contents 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Encoding of reg Field when the (w) Field is Present in Instruction.................................. 256 2-Bit sreg2 Field..................................................................................................... 256 3-Bit sreg3 Field.....................................................................................................
About this Manual—Intel® Quark Core 1.0 About this Manual This manual describes the embedded Intel® Quark SoC X1000 Core. It is intended for use by hardware designers familiar with the principles of embedded microprocessors and with the Intel® Quark SoC X1000 Core architecture. 1.1 Manual Contents Table 1 summarizes the contents of the remaining chapters and appendixes.
Intel® Quark Core—About this Manual Table 1. Manual Contents (Sheet 2 of 2) Chapter 1.2 Description Appendix A, “Signal Descriptions” Lists each Intel® Quark SoC X1000 Core signal and describes its function. Appendix B, “Testability” Describes the testability of the Intel® Quark SoC X1000 Core, including on-chip cache testing, translation lookaside buffer (TLB) testing, and JTAG.
About this Manual—Intel® Quark Core 1.3 µF microfarads pF picofarads V volts Register Bits When the text refers to more that one bit, the range of bits is represented by the highest and lowest numbered bits, separated by a colon (example: A[15:8]). The first bit shown (15 in the example) is the most-significant bit and the second bit shown (8) is the least-significant bit. Register Names Register names are shown in upper case.
Intel® Quark Core—About this Manual 1.4 Related Documents The following Intel documents contain additional information on designing systems that incorporate the Intel® Quark SoC X1000 Core. Table 2. Related Documents Ref.
Intel® Quark SoC X1000 Core Overview—Intel® Quark Core 2.0 Intel® Quark SoC X1000 Core Overview The Intel® Quark Core enables a range of low-cost, high-performance embedded system designs capable of running applications written for the Intel architecture. The Intel® Quark Core integrates a 16-Kbyte unified cache and floating-point hardware onchip for improved performance.
Intel® Quark Core—Architectural Overview 3.0 Architectural Overview 3.1 Internal Architecture The Intel® Quark Core has a 32-bit architecture with on-chip memory management and cache and floating-point units. The Intel® Quark Core also supports dynamic bus sizing for the external data bus; that is, the bus size can be specified as 8-, 16-, or 32bits wide. Note: The implementation of Intel® Quark Core on Intel® Quark SoC X1000 does not support dynamic bus sizing. Bus width is fixed at 32 bits.
Architectural Overview—Intel® Quark Core In addition to these basic data types, the Intel® Quark SoC X1000 Core supports two larger units of memory: pages and segments. Memory can be divided up into one or more variable-length segments, which can be swapped to disk or shared between programs. Memory can also be organized into one or more 4-Kbyte pages. Both segmentation and paging can be combined, gaining the advantages of both systems.
Intel® Quark Core—Architectural Overview Figure 2. Address Translation Effective Address Calculation Index Base Displacement X Scale 1, 2, 3, 4 31 BE3#–BE0# A31–A2 0 Physical Memory + Effective Address 32 15 3 2 0 Selector R P L Segmentation Unit Logical or Virtual Address 32 Linear Address Paging Unit (optional use) 32 Physical Address 13 Descriptor Index Segment Register A5158-01 3.3.2 Segment Register Usage The main data structure used to organize memory is the segment.
Architectural Overview—Intel® Quark Core 3.4 I/O Space The Intel® Quark SoC X1000 Core allows 64 K+3 bytes to be addressed within the I/O space. The Host Bridge propagates the Intel® Quark SoC X1000 Core I/O address without any translation on to the destination bus and, therefore, provides addressability for 64 K+3 byte locations. Note that the upper three locations can be accessed only during I/O address wrap-around when processor bus A16# address signal is asserted.
Intel® Quark Core—Architectural Overview 3.5.2 Register and Immediate Modes The following two addressing modes provide for instructions that operate on register or immediate operands: • Register Operand Mode: The operand is located in one of the 8-, 16- or 32-bit general registers. • Immediate Operand Mode: The operand is included in the instruction as part of the opcode. 3.5.3 32-Bit Memory Addressing Modes The remaining modes provide a mechanism for specifying the effective address of an operand.
Architectural Overview—Intel® Quark Core Based Scaled Index Mode: The contents of an INDEX register is multiplied by a SCALING factor and the result is added to the contents of a BASE register to obtain the operand's offset. Example: MOV ECX, [EDX*8] [EAX] Figure 3.
Intel® Quark Core—Architectural Overview 3.5.4 Differences Between 16- and 32-Bit Addresses In order to provide software compatibility with older processors, the Intel® Quark SoC X1000 Core can execute 16-bit instructions in Real and Protected Modes. The processor determines the size of the instructions it is executing by examining the D bit in the CS segment Descriptor. If the D bit is 0 then all operand lengths and effective addresses are assumed to be 16 bits long.
Architectural Overview—Intel® Quark Core Figure 4.
Intel® Quark Core—Architectural Overview 8-bit Integer: Signed 8-bit quantity 16-bit Integer: Signed 16-bit quantity 32-bit Integer: Signed 32-bit quantity 64-bit Integer: Signed 64-bit quantity The integer core of the Intel® Quark SoC X1000 Core only support 8-, 16- and 32-bit integers. See Section 3.6.1.4 for details. 3.6.1.3 BCD Data Types The Intel® Quark SoC X1000 Core supports packed and unpacked binary coded decimal (BCD) data types.
Architectural Overview—Intel® Quark Core 3.6.1.6 ASCII Data Types The Intel® Quark SoC X1000 Core supports ASCII (American Standard Code for Information Interchange) strings and can perform arithmetic operations (such as addition and division) on ASCII data. The Intel® Quark SoC X1000 Core can only operate on ASCII data; see Figure 6. Figure 5.
Intel® Quark Core—Architectural Overview Figure 6. String and ASCII Data Types String Data Types Address A+N A+1 Byte N String 7 0 A+2N-1 Word String 15 A+4N+3 A+4N+2 A+4N+1 Dword String 0 31 0 7 7 0 7 0 7 .... A+6 A+5 0 A+2 A+1 A 0 0 31 A A+1 0 7 A 0 15 A+3 A+4 0 0 15 31 0 7 0 A-268,435,455 A-3 A-2 A-1 0 7 ..1 0 7 +7 +2,147,483,647 A+1 1 1 A+2 A+3 A+2 0 0 7 7 A+3 0 .... A+268,435,455 Bit String A+7 A+4N N A+2N N A 1 .... 0 7 ..
Architectural Overview—Intel® Quark Core 3.6.2 Little Endian vs. Big Endian Data Formats The Intel® Quark SoC X1000 Core, as well as all other members of the Intel architecture, use the “little-endian” method for storing data types that are larger than one byte. Words are stored in two consecutive bytes in memory with the low-order byte at the lowest address and the high order byte at the high address.
Intel® Quark Core—Architectural Overview Exceptions are classified as faults, traps, or aborts, depending on the way they are reported, and whether or not restart of the instruction causing the exception is supported. Faults are exceptions that are detected and serviced before the execution of the faulting instruction. A fault would occur in a virtual memory system when the processor referenced a page or a segment that was not present.
Architectural Overview—Intel® Quark Core The IF bit in the EFLAG registers is reset when an interrupt is being serviced. This effectively disables servicing additional interrupts during an interrupt service routine. However, the IF may be set explicitly by the interrupt handler, to allow the nesting of interrupts. When an IRET instruction is executed, the original state of the IF is restored. Table 5.
Intel® Quark Core—Architectural Overview While executing the NMI servicing procedure, the Intel® Quark Core will not service further NMI requests until an interrupt return (IRET) instruction is executed or the processor is reset (RSM in the case of SMI#). If NMI occurs while currently servicing an NMI, its presence will be saved for servicing after executing the first IRET instruction. The IF bit is cleared at the beginning of an NMI interrupt to inhibit further INTR interrupts. 3.7.
Architectural Overview—Intel® Quark Core As the Intel® Quark SoC X1000 Core executes instructions, it follows a consistent cycle in checking for exceptions. Consider the case of the Intel® Quark SoC X1000 Core having just completed an instruction. It then performs the checks listed in Table 7 before reaching the point where the next instruction is completed. This cycle is repeated as each instruction is executed, and occurs in parallel with instruction decoding and execution.
Intel® Quark Core—Architectural Overview 3.7.8 Double Fault A Double Fault (exception 8) results when the Intel® Quark SoC X1000 Core attempts to invoke an exception service routine for the segment exceptions (10, 11, 12 or 13), but in the process of doing so, detects an exception other than a Page Fault (exception 14).
System Register Organization—Intel® Quark Core 4.0 System Register Organization 4.
Intel® Quark Core—System Register Organization Note: In register descriptions, “set” means “set to 1,” and “reset” means “set to 0.” Figure 9. Base Architecture Registers General Purpose Registers 31 24 23 16 15 0 8 7 AH AX AL EAX BH BX BL EBX CH BX CL ECX DH DX DL EDX ESI EDI EBP ESP Segment Registers 15 0 CS Code Segment SS Stack Segment DS ES Data Segments FS GS Instruction Pointer 31 16 15 0 IP EIP Flags Register FLAGS EFLAGS A5144-01 4.3.
System Register Organization—Intel® Quark Core The least significant 16 bits of the general purpose registers can be accessed separately using the 16-bit names of the registers AX, BX, CX, DX, SI, DI, BP and SP. The upper 16 bits of the register are not changed when the lower 16 bits are accessed separately. Finally, 8-bit operations can individually access the lower byte (bits 7:0) and the highest byte (bits 15:8) of the general purpose registers AX, BX, CX and DX.
Intel® Quark Core—System Register Organization ID (Identification Flag, bit 21) The ability of a program to set and clear the ID flag indicates that the processor supports the CPUID instruction. Refer to Chapter 12.0, “Instruction Set Summary” and Appendix C, “Feature Determination.” VIP (Virtual Interrupt Pending Flag, bit 20) The VIP flag together with the VIF enable each applications program in a multitasking environment to have virtualized versions of the system's IF flag.
System Register Organization—Intel® Quark Core X1000 Core does not cause any AC faults when the effective address given in the instruction has the proper alignment. VM (Virtual 8086 Mode, bit 17) The VM bit provides Virtual 8086 Mode within Protected Mode. When the VM bit is set while the Intel® Quark SoC X1000 Core is in Protected Mode, the Intel® Quark SoC X1000 Core switches to Virtual 8086 operation, handling segment loads and generating exception 13 faults on privileged opcodes.
Intel® Quark Core—System Register Organization IF (INTR Enable Flag, bit 9) The IF flag, when set, allows recognition of external interrupts signaled on the INTR pin. When IF is reset, external interrupts signaled on the INTR are not recognized. IOPL indicates the maximum CPL value allowing alteration of the IF bit when new values are popped into EFLAGS or FLAGS. TF (Trap Enable Flag, bit 8) TF controls the generation of the exception 1 trap when the processor is singlestepping through code.
System Register Organization—Intel® Quark Core Intel® Quark SoC X1000 Core Segment Registers and Associated Descriptor Cache Registers Figure 11.
Intel® Quark Core—System Register Organization Figure 12. System-Level Registers 31 24 23 16 15 8 7 0 CR0 Page Fault Linear Address Register CR2 Page Directory Base Register CR3 CR4 32-Bit Linear Base Address 47 16 15 Limit GDTR Selector IDTR Selector System Segment Registers 15 Descriptor Registers (Loaded Automatically) 0 TR Selector LDTR Selector 0 32-Bit Linear Base Address 20-Bit Segment Limit Attributes A5148-01 4.4.
System Register Organization—Intel® Quark Core Figure 13. Control Registers 4.4.1.1 Control Register 0 (CR0) CR0, shown in Figure 13, contains 10 bits for control and status purposes. The function of the bits in CR0 can be categorized as follows: • Intel® Quark SoC X1000 Core Operating Modes: PG, PE (Table 10) • On-Chip Cache Control Modes: CD, NW (Table 11) • On-Chip Floating-Point Unit: NE, TS, EM, TS (Table 12 and Table 13). (Also applies for the Intel® Quark SoC X1000 Core.
Intel® Quark Core—System Register Organization Table 10. Table 11. Intel® Quark SoC X1000 Core Operating Modes PG PE Mode 0 0 Real Mode. 32-bit extensions available with prefixes. 0 1 Protected Mode. 32-bit extensions through both prefixes and “default” prefix setting associated with code segment descriptors. Also, a sub-mode is defined to support a virtual 8086 processor within the context of the extended processor protection model. 1 0 Undefined.
System Register Organization—Intel® Quark Core reach the external bus are cache misses. Write hits with NW=1 never update main memory. Invalidate cycles are ignored when NW=1. AM (Alignment Mask, bit 18) Enables automatic alignment checking when set; disables alignment checking when clear. Alignment checking is performed only when the AM flag is set, the AC flag in the EFLAGS register is set, CPL is 3, and the processor is operating in either protected or virtual-8086 mode.
Intel® Quark Core—System Register Organization TS (Task Switch, bit 3) • Intel® Quark SoC X1000 Core TS bit: For Intel® Quark SoC X1000 Core, the TS bit is set whenever a task switch operation is performed. Execution of floating-point instructions with TS=1 causes a Device Not Available (DNA) fault (trap vector 7). If TS=1 and MP=1 (monitor coprocessor in CR0), a WAIT instruction causes a DNA fault.
System Register Organization—Intel® Quark Core Table 13. Interpreting Different Combinations of EM, TS and MP Bits (Sheet 2 of 2) CR0 Bit Note: 4.4.1.2 Instruction Type EM TS MP Floating-Point Wait 1 0 1 Exception 7 Execute 1 1 0 Exception 7 Execute 1 1 1 Exception 7 Exception 7 For Intel® Quark SoC X1000 Core, when MP=1 and TS=1, the processor generates a trap 7 so that the system software can save the floating-point status of the old task.
Intel® Quark Core—System Register Organization instructions allow the control registers to be read or loaded (at privilege level 0 only). This restriction means that application programs or operating system procedures (running at privilege levels 1, 2, or 3) are prevented from reading or loading the control registers. Figure 14. Intel® Quark SoC X1000 Core CR4 Register Flags relevant to Intel® Quark SoC X1000 Core are described below.
System Register Organization—Intel® Quark Core 4.5 Floating-Point Registers Figure 15 shows the floating-point register set. The on-chip FPU contains eight data registers, a tag word, a control register, a status register, an instruction pointer and a data pointer. 4.5.1 Floating-Point Data Registers Floating-point computations use the Intel® Quark SoC X1000 Core FPU data registers. These eight 80-bit registers provide the equivalent capacity of twenty 32-bit registers.
Intel® Quark Core—System Register Organization 4.5.2 Floating-Point Tag Word The tag word marks the content of each numeric data register, as shown in Figure 16. Each two-bit tag represents one of the eight data registers. The principal function of the tag word is to optimize the FPU’s performance and stack handling by making it possible to distinguish between empty and non-empty register locations.
System Register Organization—Intel® Quark Core Figure 17. Floating-Point Status Word Busy Top of Stack Pointer Condition Code 15 7 B C 3 TOP C 2 C 1 C 0 0 E S S F P E U E O E Z E D E I E Error Summary Status Stack Flag Exception Flags: Precision Underflow Overflow Zero Divide Denormalized Operand Invalid Operation ES is set if any unmasked exception bit is set; cleared otherwise. See Table 14 4-7for forinterpretation interpretationofofcondition conditioncode. code.
Intel® Quark Core—System Register Organization Table 14. Condition Code Interpretation after FPREM and FPREM1 Instructions Condition Code Interpretation after FPREM and FPREM1 C2 C3 C1 C0 1 X X X Q1 Q0 Q2 Q MOD8 0 0 0 0 0 1 0 1 0 Table 15.
System Register Organization—Intel® Quark Core Table 16. Table 17.
Intel® Quark Core—System Register Organization Section 4.5.4. Note that when a new value is loaded into the status word by the FLDENV (load environment) or FRSTOR (restore state) instruction, the value of ES (bit 7) and its reflection in the B bit (bit 15) are not derived from the values loaded from memory. The values of ES and B are dependent upon the values of the exception flags in the status word and their corresponding masks in the control word.
System Register Organization—Intel® Quark Core Figure 18. Protected Mode FPU Instructions and Data Pointer Image in Memory (32-Bit Format) 32-Bit Protected Mode Format 31 23 15 7 0 Intel Reserved Control Word 0 Intel Reserved Status Word 4 Intel Reserved Tag Word 8 c IP Offset CS Selector OPCODE 10..0 0000 10 14 Data Operand Offset Intel Reserved 18 Operand Selector A5153-01 Figure 19.
Intel® Quark Core—System Register Organization Figure 20. Protected Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format) 16-Bit Protected Mode Format 15 7 0 Control Word 0 Status Word 2 Tag Word 4 IP Offset 6 CS Selector 8 Operand Offset A Operand Selector C A5155-01 Figure 21. Real Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format) 16-Bit Real Address Mode and Virtual-8086 Mode Format 15 7 IP19.
System Register Organization—Intel® Quark Core Figure 22. FPU Control Word Reserved Reserved† Rounding Control Precision Control 15 7 X X X X RC PC 0 X X P M U O M M Reserved Exception Masks: Precision Underflow Overflow Zero Divide Denormalized Operand Invalid Operation Precision Control: 00-24 bits (single precision) 01- (reserved) 10-53 bits (double precision) 11-64 bits (extended precision) Z M D I M M † "0" after reset or FINIT; changeable upon loading the control word (CW).
Intel® Quark Core—System Register Organization affects only the instructions ADD, SUB, DIV, MUL, and SQRT. For all other instructions, either the precision is determined by the opcode or extended precision is used. 4.6 Debug and Test Registers 4.6.1 Debug Registers The programmer accessible debug registers in Table 19 provide on-chip support for debugging. Debug registers DR[3:0] specify the four linear breakpoints.
System Register Organization—Intel® Quark Core 4.7.1 FPU Register Usage In addition to the differences listed in Table 21, Table 22 summarizes the differences for the on-chip FPU. Table 21.
Intel® Quark Core—System Register Organization • Do not depend on the ability to retain information written into any reserved bits. • When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. Note: Avoid any software dependence upon the state of reserved bits in Intel® Quark SoC X1000 Core registers.
Real Mode Architecture—Intel® Quark Core 5.0 Real Mode Architecture 5.1 Introduction When the Intel® Quark SoC X1000 Core is powered up or reset, it is initialized in Real Mode. Real Mode allows access to the 32-bit register set of the Intel® Quark SoC X1000 Core. All of the Intel® Quark SoC X1000 Core instructions are available in Real Mode (except those instructions listed in Section 6.5.4, “Protection and I/O Permission Bitmap” on page 109). The default operand size in Real Mode is 16 bits.
Intel® Quark Core—Real Mode Architecture 5.2 Memory Addressing In Real Mode, the maximum memory size is limited to 1 Mbyte. (See Figure 23.) Thus, only address lines A[19:2] are active with this exception: after RESET address lines A[31:20] are high during CS-relative memory cycles until an intersegment jump or call is executed. See Section 9.5, “Reset and Initialization” on page 169. Figure 23.
Real Mode Architecture—Intel® Quark Core 5.4 Interrupts Many of the exceptions discussed in Section 3.7.3, “Maskable Interrupt” on page 34 are not applicable to Real Mode operation, in particular exceptions 10, 11, 14, and 17, which do not occur in Real Mode. Other exceptions have slightly different meanings in Real Mode; Table 25 identifies these exceptions. 5.
Intel® Quark Core—Protected Mode Architecture 6.0 Protected Mode Architecture The full capabilities of the Intel® Quark SoC X1000 Core are available when it operates in Protected Virtual Address Mode (Protected Mode). Protected Mode vastly increases the linear address space to four Gbytes (232 bytes) and allows the processor to run virtual memory programs of almost unlimited size (64 terabytes or 246 bytes).
Protected Mode Architecture—Intel® Quark Core Figure 24. Protected Mode Addressing Figure 25. Paging and Segmentation 6.2 Segmentation 6.2.1 Segmentation Introduction Segmentation is one method of memory management. Segmentation provides the basis for protection. Segments are used to encapsulate regions of memory that have common attributes. For example, all of the code of a given program could be contained in a segment, or an operating system table may reside in a segment.
Intel® Quark Core—Protected Mode Architecture 6.2.2 Terminology The following terms are used throughout the discussion of descriptors, privilege levels and protection: PL: Privilege Level One of the four hierarchical privilege levels. Level 0 is the most privileged level and level 3 is the least privileged. Higher privilege levels are numerically smaller than lower privilege levels. RPL: Requester Privilege Level The privilege level of the original supplier of the selector.
Protected Mode Architecture—Intel® Quark Core Figure 26. Descriptor Table Registers 6.2.3.2 Global Descriptor Table The Global Descriptor Table (GDT) contains descriptors that are possibly available to all of the tasks in a system. The GDT can contain any type of segment descriptor except for descriptors that are used for servicing interrupts (i.e., interrupt and trap descriptors). Every Intel® Quark SoC X1000 Core system contains a GDT.
Intel® Quark Core—Protected Mode Architecture Figure 27. Interrupt Descriptor Table Register Use Memory Gate for Interrupt #n Gate for Interrupt #n-1 Interrupt Descriptor Table (DT) Processor 15 0 IDT Limit Gate for Interrupt #1 Gate for Interrupt #0 Increasing Memory Addresses IDT Base 31 0 A5212-01 6.2.4 Descriptors 6.2.4.1 Descriptor Attribute Bits The object to which the segment selector points to is called a descriptor.
Protected Mode Architecture—Intel® Quark Core granularity is unrelated to paging. A Intel® Quark SoC X1000 Core system can consist of segments with byte granularity and page granularity, whether or not paging is enabled. The executable (E) bit tells if a segment is a code or data segment. A code segment (E=1, S=1) may be execute-only or execute/read as determined by the Read (R) bit. Code segments are execute-only if R=0, and execute/read if R=1. Code segments may never be written to.
Intel® Quark Core—Protected Mode Architecture Table 26. Access Rights Byte Definition for Code and Data Descriptions Bit Position 7 6–5 Name Function P=1 P=0 Present (P) Descriptor Privilege Level (DPL) Segment is mapped into physical memory. No mapping to physical memory exits, base and limit are not used. Segment privilege attribute used in privilege tests. 4 Segment Descriptor (S) S=1 S=0 Code or Data (includes stacks) segment descriptor. System Segment Descriptor or Gate Descriptor.
Protected Mode Architecture—Intel® Quark Core Figure 29. System Segment Descriptors 31 16 0 Segment Base 15...0 Base 31...24 G 0 Type 0 6.2.4.4 0 0 Segment Limit 15...0 Limit 19...16 P DPL Defines Invalid 0 Type Type Byte Address 0 Base 23...
Intel® Quark Core—Protected Mode Architecture parameters are to be copied from the caller's stack to the stack of the called routine. The word count field is only used by call gates when there is a change in the privilege level; other types of gates ignore the word count field. Figure 30. Gate Descriptor Formats 31 24 16 8 Selector 5 0 Offset 15...0 Offset 31...16 P DPL 0 Type 0 0 0 Word Count 4...
Protected Mode Architecture—Intel® Quark Core 6.2.4.7 Selector Fields A selector in Protected Mode has three fields: Local or Global Descriptor Table Indicator (TI), Descriptor Entry Index (Index), and Requester (the selector's) Privilege Level (RPL) as shown in Figure 31. The TI bits select one of two memory-based tables of descriptors (the Global Descriptor Table or the Local Descriptor Table). The Index selects one of 8 K descriptors in the appropriate descriptor table.
Intel® Quark Core—Protected Mode Architecture Figure 31.
Protected Mode Architecture—Intel® Quark Core Figure 32.
Intel® Quark Core—Protected Mode Architecture Figure 33.
Protected Mode Architecture—Intel® Quark Core Figure 34. Segment Descriptor Caches for Virtual 8086 Mode within Protected Mode (Segment Limit and Attributes are Fixed) Key: Y = N = 0 = 1 = 2 = 3 = U = yes no privilege level privilege level privilege level privilege level expand up 0 1 2 3 D B P W F – = = = = = = expand down byte granularity page granularity push/pop 16-bit words push/pop 32-bit dwords does not apply to that segment cache register 6.3 Protection 6.3.
Intel® Quark Core—Protected Mode Architecture Figure 35. Four-Level Hierarchical Protection 6.3.2 Rules of Privilege The Intel® Quark SoC X1000 Core controls access to both data and procedures between levels of a task, according to the following rules. • Data stored in a segment with privilege level p can be accessed only by code executing at a privilege level at least as privileged as p.
Protected Mode Architecture—Intel® Quark Core 6.3.3.3 I/O Privilege and I/O Permission Bitmap The I/O privilege level (IOPL, a 2-bit field in the EFLAG register) defines the least privileged level at which I/O instructions can be unconditionally performed. I/O instructions can be unconditionally performed when CPL ≥ IOPL. (The I/O instructions are IN, OUT, INS, OUTS, REP INS, and REP OUTS.
Intel® Quark Core—Protected Mode Architecture Figure 36.
Protected Mode Architecture—Intel® Quark Core Figure 37. Sample I/O Permission Bit Map I/O Ports Accessible: 2-9, 12, 13, 15, 20-24, 27, 33, 34, 40, 41, 48, 50, 52, 53, 58-60, 62, 63, 96-127 The IOPL also affects whether the IF (interrupts enable flag) bit can be changed by loading a value into the EFLAGS register. When CPL ≥ IOPL, the IF bit can be changed by loading a new value into the EFLAGS register.
Intel® Quark Core—Protected Mode Architecture Any time an instruction loads data segment registers (DS, ES, FS, GS) the Intel® Quark SoC X1000 Core makes protection validation checks. Selectors loaded in the DS, ES, FS, GS registers must refer only to data segments or readable code segments. (The data access rules are specified in Section 6.3.2. The only exception to those rules is readable conforming code segments, that can be accessed at any privilege level.
Protected Mode Architecture—Intel® Quark Core The privilege rules require that: • Privilege level transitions can only occur via gates. • JMPs can be made to a non-conforming code segment with the same privilege or to a conforming code segment with greater or equal privilege. • CALLs can be made to a non-conforming code segment with the same privilege or via a gate to a more privileged level. • Interrupts handled within the task obey the same privilege rules as CALLs.
Intel® Quark Core—Protected Mode Architecture Interrupt gates and trap gates work in a similar fashion as the call gates, except there is no copying of parameters. The only difference between trap and interrupt gates is that control transfers through an interrupt gate disable further interrupts (i.e., the IF bit is set to 0), and trap gates leave the interrupt status unchanged. 6.3.
Protected Mode Architecture—Intel® Quark Core Each task must have a TSS associated with it. The current TSS is identified by a special register in the Intel® Quark SoC X1000 Core called the Task State Segment Register (TR). This register contains a selector referring to the task state segment descriptor that defines the current TSS. A hidden base register and limit register associated with TR are loaded whenever TR is loaded with a new selector.
Intel® Quark Core—Protected Mode Architecture a simple Protected Mode Intel® Quark SoC X1000 Core system. It has a single code and single data/stack segment, each four-Gbytes long, and a single privilege level, PL = 0. The actual method of enabling Protected Mode is to load CR0 with the PE bit set via the MOV CR0, R/M instruction. After enabling Protected Mode, the next instruction should execute an intersegment JMP to load the CS register and flush the instruction decode queue.
Protected Mode Architecture—Intel® Quark Core Figure 40. GDT Descriptors for Simple System 2 Data Descriptor Base 31...24 00(H) G 1 D 1 0 0 Limit 19.16 F(H) Segment Base 15...0 0118(H) 1 Code Descriptor Base 31...24 00(H) G 1 D 1 1 0 0 1 0 0 1 0 Base 23...16 00(H) 1 Base 23...16 00(H) Segment Base 15...0 FFFF(H) 0 0 Limit 19.16 F(H) Segment Base 15...0 0118(H) 1 0 0 1 0 0 1 Segment Base 15...0 FFFF(H) NULL DESCRIPTOR 0 31 6.4 Paging 6.4.
Intel® Quark Core—Protected Mode Architecture 6.4.2.3 Page Directory The Page Directory is 4 Kbytes long and allows up to 1024 page directory entries. Each page directory entry contains the address of the next level of tables, the Page Tables and information about the page table. The upper 10 bits of the linear address (A[31:22]) are used as an index to select the correct page directory entry. 6.4.2.4 Page Tables Each Page Table is 4 Kbytes and holds up to 1024 page table entries.
Protected Mode Architecture—Intel® Quark Core CR4.PGE enables global pages. If CR4.PGE = 0, no translations are shared across address spaces; if CR4.PGE = 1, specified translations may be shared across address spaces. CR4.SMEP allows pages to be protected from supervisor-mode instruction fetches. If CR4.SMEP = 1, software operating in supervisor mode cannot fetch instructions from linear addresses that are accessible in user mode. IA32_EFER.NXE enables execute-disable access rights for PAE paging.
Intel® Quark Core—Protected Mode Architecture Note: On some processors, reserved bits are checked even in PDPTEs in which the P flag (bit 0) is 0. Table 30.
Protected Mode Architecture—Intel® Quark Core comprises 512 64-bit entries (PTEs). A PTE is selected using the physical address defined as follows: — Bits 31:12 are from the PDE. — Bits 11:3 are bits 20:12 of the linear address. — Bits 2:0 are 0. • Because a PTE is identified using bits 31:12 of the linear address, every PTE maps a 4-KByte page (see Table 33). The final physical address is computed as follows: — Bits 31:12 are from the PTE. — Bits 11:0 are from the original linear address.
Intel® Quark Core—Protected Mode Architecture Figure 42. Linear-Address Translation to a 2-MByte Page using PAE Paging Table 31.
Protected Mode Architecture—Intel® Quark Core Table 32. Format of a PAE Page-Directory Entry that References a Page Table Bit Position(s) Table 33.
Intel® Quark Core—Protected Mode Architecture Figure 43 and Figure 44 show a summary of the formats of CR3 and the pagingstructure entries with PAE paging. For the paging structure entries, it identifies separately the format of entries that map pages, those that reference other paging structures, and those that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted because they determine how a paging-structure entry is used. Figure 43.
Protected Mode Architecture—Intel® Quark Core Figure 44.
Intel® Quark Core—Protected Mode Architecture 6.4.4 #GP Faults for Intel® Quark SoC X1000 Core Failures to load the PDPTE registers with PAE paging causes #GP fault. • If any of the PDPTEs sets both the P flag (bit 0) and any reserved bit, it causes a general-protection exception (#GP(0)) and the PDPTEs are not loaded. • If any of the PDPTE entries have P flag (bit 0) cleared and any of the reserved bits are set this does not cause #GP(0) fault.
Protected Mode Architecture—Intel® Quark Core If CR4.SMEP = 1, instructions may be fetched from any linear address with a valid translation for which the U/S flag (bit 2) is 0 in at least one of the pagingstructure entries controlling the translation. — For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, access rights depend on the value of CR4.SMEP: If CR4.
Intel® Quark Core—Protected Mode Architecture — The I/D bit of the page fault error code (bit 4) will be set when an instruction page faults occurs and CR4.SMEP. It may also be set in other cases. • CR4.SMEP is zero by default: set to zero on RESET • CPUID >3 <8000_0000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[22] = 1’b0. • Requires supporting IA32_MISC_ENABLE Model Specific Register (MSR). 6.4.5.1.1 Instruction Fetches Access Rights in Supervisor Mode (CPL <3) For 32-bit paging when IA32_EFER.
Protected Mode Architecture—Intel® Quark Core Table 34.
Intel® Quark Core—Protected Mode Architecture Figure 45. Translation Lookaside Buffer Reading a new entry into the TLB (TLB refresh) is a two step process handled by the Intel® Quark SoC X1000 Core hardware. The sequence of data cycles to perform a TLB refresh is as follows: 1. Read the correct page directory entry, as pointed to by the page base register and the upper 10 bits of the linear address. The page base register is in Control Register 3.
Protected Mode Architecture—Intel® Quark Core Figure 46 illustrates the error code that the processor provides on delivery of a pagefault exception. Figure 46. Page-Fault Error Code The following items explain how the bits in the error code describe the nature of the page-fault exception: • P flag (bit 0). This flag is 0 if there is no valid translation for the linear address because the P flag was 0 in one of the paging-structure entries used to translate that address. • W/R (bit 1).
Intel® Quark Core—Protected Mode Architecture • I/D flag (bit 4). This flag is 1 if (1) the access causing the page-fault exception was an instruction fetch; and (2) either (a) CR4.SMEP = 1; or (b) both (i) CR4.PAE = 1 (either PAE paging or IA-32e paging is in use); and (ii) IA32_EFER.NXE = 1. Otherwise, the flag is 0. This flag describes the access causing the page-fault exception, not the access rights specified by paging. Page-fault exceptions occur only due to an attempt to use a linear address.
Protected Mode Architecture—Intel® Quark Core Figure 47. Page Fault System Information 15 U U U U U U U U U U U U/S W/R 0 0 Supervisor† Read 0 1 Supervisor Write 1 0 User Read 1 1 User Write U 3 2 1 0 U US WR P Access Type † Descriptor table access faults with U/S = 0, even if the program is executing at level 3.
Intel® Quark Core—Protected Mode Architecture Figure 48. Virtual 8086 Environment Memory Management 3K\VLFDO 0HPRU\ + 3DJH 1 26 (PSW\ 7DVN 3DJH 7DEOH 9LUWXDO 0RGH 7DVN 3DJH 'LUHFWRU\ 7DVN $YDLODEOH 3DJH 1 3DJH 26 + (PSW\ 3DJH 'LUHFWRU\ 5RRW 9LUWXDO 0RGH 7DVN 7DVN 3DJH 7DEOH 3DJH 'LUHFWRU\ 7DVN 7DVN 0HPRU\ 7DVN 0HPRU\ /DNHPRQW &RUH 26 0HPRU\ 26 0HPRU\ 6.5.
Protected Mode Architecture—Intel® Quark Core The paging hardware allows the 20-bit linear address produced by a Virtual Mode program to be divided into up to 256 pages. Each one of the pages can be located anywhere within the maximum 4-Gbyte physical address space of the Intel® Quark SoC X1000 Core. In addition, because CR3 (the Page Directory Base Register) is loaded by a task switch, each Virtual Mode task can use a different mapping scheme to map pages to different physical locations.
Intel® Quark Core—Protected Mode Architecture Note that the I/O instructions (IN, OUT, INS, OUTS, REP INS, and REP OUTS) are not IOPL-sensitive in Virtual 8086 Mode. Rather, the I/O instructions become automatically sensitive to the I/O permission bitmap contained in the Intel® Quark SoC X1000 Core Task State Segment. The I/O permission bitmap, automatically used by the Intel® Quark SoC X1000 Core in Virtual 8086 Mode, is illustrated by Figure 36 and Figure 37.
Protected Mode Architecture—Intel® Quark Core An Intel® Quark SoC X1000 Core operating system can provide a Virtual 8086 environment that is totally transparent to the application software by intercepting and then emulating the legacy operating system's calls, and intercepting IN and OUT instructions. Figure 49.
Intel® Quark Core—Protected Mode Architecture The VM bit can be set by executing an IRET instruction only at privilege level 0, or by any instruction or interrupt that causes a task switch in Protected Mode (with VM=1 in the new FLAGS image). The UM bit can be cleared only by an interrupt or exception in Virtual 8086 Mode. IRET and POPF instructions executed in Real Mode or Virtual 8086 Mode do not change the value in the VM bit.
Protected Mode Architecture—Intel® Quark Core 3. Push the legacy segment register values onto the new stack, in the order: GS, FS, DS, ES. These are pushed as 32-bit quantities, with undefined values in the upper 16 bits. Then, load these four registers with null selectors (0). 4. Push the old stack pointer onto the new stack by pushing the SS register (as 32-bits, high bits undefined), then pushing the 32-bit ESP register saved above. 5. Push the 32-bit FLAGS register saved in step 1. 6.
Intel® Quark Core—On-Chip Cache 7.0 On-Chip Cache The Intel® Quark SoC X1000 Core processor has a 16-Kbyte cache, as discussed in Section 7.1.1. The cache is software-transparent to maintain binary compatibility with previous generations of the Intel Architecture. The on-chip cache is designed for maximum flexibility and performance. The cache has several operating modes, offering flexibility during program execution and debugging.
On-Chip Cache—Intel® Quark Core The Write-Back Enhanced Intel® Quark SoC X1000 Core supports two modes of operation with respect to internal cache configurations: Standard Bus Mode (writethrough cache) and Enhanced Bus Mode (write-back cache). See Section 7.1.1 and other write-back enhanced sections below for write-back cache information. 7.1.
Intel® Quark Core—On-Chip Cache Table 36. 7.2 Cache Operating Modes CD NW Operating Mode 1 1 1 0 Cache fills disabled, write-through and invalidates enabled. 0 1 INVALID. When CR0 is loaded with this configuration of bits, a GP fault with error code of 0 is raised. 0 0 Cache fills enabled, write-through and invalidates enabled. Cache fills disabled, write-through and invalidates disabled. Cache Control Control of the cache is provided by the CD and NW bits in CR0.
On-Chip Cache—Intel® Quark Core CD=1, NW=1 The 1,1 state is best used when no lines are allocated, which occurs naturally after RESET (but not SRESET), but must be forced (e.g., by the WBINVD instruction) when entered during normal operation. In these cases, the Write-Back Enhanced Intel® Quark SoC X1000 Core operates as if it had no cache at all. When the 1,1 state is exited, lines that are allocated as write-back are written back upon a snoop hit or replacement cycle.
Intel® Quark Core—On-Chip Cache 7.4 Cache Line Invalidations The Intel® Quark SoC X1000 Core contains both a hardware and software mechanism for invalidating internal cache lines. Cache line invalidations are needed to keep the cache contents consistent with external memory. Refer to Section 10.3.8, “Invalidate Cycles” on page 213 for further information. 7.4.
On-Chip Cache—Intel® Quark Core The pseudo LRU mechanism works in the following manner: When a line must be replaced, the cache first selects which of lines 11:10 and 13:12 was least recently used. Then the cache determines which of the two lines was least recently used and mark it for replacement. This decision tree is shown in Figure 51. Table 38.
Intel® Quark Core—On-Chip Cache The state of the PCD bit in the page table entry is driven on the PCD pin when a page in external memory is accessed. The state of the PCD pin informs the external system of the cacheability of the requested information. The external system then returns KEN#, telling the Intel® Quark SoC X1000 Core whether the area is cacheable. The Intel® Quark SoC X1000 Core initiates a cache line fill when PCD and KEN# indicate that the requested information is cacheable.
On-Chip Cache—Intel® Quark Core Figure 52. Page Cacheability C D CR0 N W FLUSH# Cache Control Logic KEN# Cache Memory 31 Linear Address 31 22 Directory 12 Table 0 Offset PCD PCD 10 10 PWT 0 31 CR0 31 0 CR1 + PCD, PWT + 0 PCD, PWT CR2 CR3 PCD, PWT Control Registers 7.6.
Intel® Quark Core—On-Chip Cache 7.7 Cache Flushing The on-chip cache can be flushed by external hardware or by software instructions. Flushing the cache clears all valid bits for all lines in the cache. The cache is flushed when external hardware asserts the FLUSH# pin. The FLUSH# pin must to be asserted for one clock when driven synchronously or for two clocks when driven asynchronously. FLUSH# is asynchronous, but setup and hold times must be met for recognition in a particular cycle.
On-Chip Cache—Intel® Quark Core Snoop cycles with invalidation (INV=1) cause the Write-Back Enhanced Intel® Quark SoC X1000 Core to invalidate an individual cache line. When the snooped line is a modified line, then the processor schedules a write-back cycle. Inquire cycles with noinvalidation cause the Write-Back Enhanced Intel® Quark SoC X1000 Core only to write-back the line, when the inquired line is in M-state, and not invalidate the line.
Intel® Quark Core—On-Chip Cache With the modified MESI protocol it is assumed that in a uniprocessor system, lines are defined as write-back or write-through at allocation time. This property associated with a line is never altered. The lines allocated as write-through go to S-state and remain in S-state. A cache line that is allocated as write-back never enters the S-state. The WB/WT# pin is sampled during line allocation and is used strictly to characterize a line as write-back or write-through.
On-Chip Cache—Intel® Quark Core Table 40. Cache State Transitions for Write-Back Enhanced Intel® Quark SoC X1000 Core-Initiated Write Cycles Present State Pin Activity Next State M n/a M Write hit; update cache. No bus cycle generated to update memory. Description E n/a M Write hit; update cache only. No bus cycle generated; line is now modified. S n/a S Write hit; cache updated with write data item. A write-through cycle is generated on the bus to update memory.
Intel® Quark Core—On-Chip Cache A software mechanism to determine whether a processor has write-back support for the on-chip cache should drive the WB/WT# pin to ‘1’ during RESET. This pin is sampled by the processor during the falling edge of RESET. Execute the CPUID instruction, which returns the model number in the EAX register, EAX[7:4].
System Management Mode (SMM) Architectures—Intel® Quark Core 8.0 System Management Mode (SMM) Architectures 8.1 SMM Overview The Intel® Quark SoC X1000 Core supports four modes: Real, Virtual-86, Protected, and System Management Mode (SMM). As an operating mode, SMM has a distinct processor environment, interface and hardware/software features.
Intel® Quark Core—System Management Mode (SMM) Architectures 8.3 SMBASE Control register that contains the address of the SMRAM space. Context The processor state just before the processor invokes SMM. The context normally consists of the processor registers that fully represent the processor state. Context Switch The process of either saving or restoring the context.
System Management Mode (SMM) Architectures—Intel® Quark Core The System Management Interrupt hardware interface consists of the SMI# interrupt request input and the SMIACT# output the system uses to decode the SMRAM. Figure 54. Basic SMI# Hardware Interface CPU 8.3.1 } SMI Interface System Management Interrupt (SMI#) SMI# is a falling-edge triggered, non-maskable interrupt request signal.
Intel® Quark Core—System Management Mode (SMM) Architectures The number of CLKs required to complete the SMM state save and restore is dependent on-system memory performance. The values listed in Table 42 assume zero wait-state memory writes (two CLK cycles), 2-1-1-1 burst read cycles, and zero wait-state nonburst reads (2 CLK cycles). Additionally, it is assumed that the data read during the SMM state restore sequence is not cacheable. Figure 55.
System Management Mode (SMM) Architectures—Intel® Quark Core The processor asserts the SMIACT# output to indicate to the memory controller that it is operating in System Management Mode. The system logic should ensure that only the processor has access to this area. Alternate bus masters or DMA devices that try to access the SMRAM space when SMIACT# is active should be directed to system RAM in the respective area.
Intel® Quark Core—System Management Mode (SMM) Architectures Figure 57.
System Management Mode (SMM) Architectures—Intel® Quark Core Table 42.
Intel® Quark Core—System Management Mode (SMM) Architectures Auto HALT Restart. It is possible for the SMI# request to interrupt the HALT state. The SMI# handler can tell the RSM instruction to return control to the HALT instruction or to return control to the instruction following the HALT instruction by appropriately setting the Auto HALT Restart slot. The default operation is to restart the HALT instruction. I/O Trap Restart.
System Management Mode (SMM) Architectures—Intel® Quark Core Figure 58. Transition to and from System Management Mode Real Mode Reset or RSM Reset or PE=0 Reset SMI# Protected Mode RSM VM=0 SMI# PE=1 VM=1 System Management Mode SMI# RSM Virtual - 86 Mode Note: Reset could occur by asserting the RESET or SRESET pin. A5234-01 The external signal SMI# causes the processor to switch to SMM. The RSM instruction exits SMM.
Intel® Quark Core—System Management Mode (SMM) Architectures When the processor invokes SMM, the processor core registers are initialized as shown in Table 43. Table 43.
System Management Mode (SMM) Architectures—Intel® Quark Core The EM bit is cleared so that no exceptions are generated. (If the SMM was entered from Protected Mode, the Real Mode interrupt and exception support is not available.) The SMI# handler should not use floating-point unit instructions until the FPU is properly detected (within the SMI# handler) and the exception support is initialized.
Intel® Quark Core—System Management Mode (SMM) Architectures 8.5 SMM Features 8.5.1 SMM Revision Identifier The SMM revision identifier is used to indicate the version of SMM and the SMM extensions supported by the processor. The SMM revision identifier is written during SMM entry and can be examined in SMRAM space at register offset 7EFCH. The lower word of the SMM revision identifier refers to the version of the base SMM architecture.
System Management Mode (SMM) Architectures—Intel® Quark Core instruction is executed (see Figure 60 and Table 45). Figure 60. Auto HALT Restart 1 15 0 Register Offset 7F02H Intel Reserved Auto HALT Restart Table 45. Bit Values for Auto HALT Restart Value of Bit 0 at Entry Value of Bit 0 at Exit 0 0 Returns to next instruction in interrupted program. 0 1 Unpredictable. 1 0 Returns to next instruction after HALT. 1 1 Returns to HALT state.
Intel® Quark Core—System Management Mode (SMM) Architectures Table 46. I/O Instruction Restart Value Value at Entry Value at Exit Comments 00H 00H Do not restart trapped I/O instruction 00H 0FFH Restart trapped I/O instruction If the system executes back-to-back SMI# requests, the second SMM handler must not set the I/O instruction restart slot (see Section 8.6.6). 8.5.4 SMM Base Relocation The Intel® Quark SoC X1000 Core provides a control register, SMBASE.
System Management Mode (SMM) Architectures—Intel® Quark Core To change the SMRAM base address and SMM jump vector location, the SMM handler should modify the SMBASE slot. Upon executing an RSM instruction, the processor reads the SMBASE slot and stores it internally. Upon recognition of the next SMI# request, the processor uses the new SMBASE slot for the SMRAM dump and SMI# jump vector.
Intel® Quark Core—System Management Mode (SMM) Architectures If SMRAM is located in its own distinct memory space, that can be completely decoded using only the processor address signals, it is said to be non-overlaid. In this case, there are no new requirements for maintaining cache coherency. Figure 64. SMRAM Location SMRAM Normal Memory SMRAM Normal Memory Shadowed Region Normal Memory Non-overlaid (no need to flush caches) Overlaid (caches must be flushed) 8.6.
System Management Mode (SMM) Architectures—Intel® Quark Core Figure 65. FLUSH# Mechanism during SMM SMI# Instr Instr Instr Instr Instr #1 #2 #3 #4 #5 State Slave State Resume SMM Handler SMI# SMIACT# RSM Flush cache Cache must be empty Cache must be empty A5237-01 The FLUSH# and KEN# signals can be used to ensure cache coherency when switching between normal and SMM modes. Cache flushing during SMM entry is accomplished by asserting the FLUSH# pin when SMI# is driven active.
Intel® Quark Core—System Management Mode (SMM) Architectures Figure 67. Non-Cached SMM State Slave SMM Handler State Resume Normal Cycle SMI# RSM SMIACT# KEN# FLUSH# A5239-01 8.6.2.1 Write-Back Enhanced Intel® Quark SoC X1000 Core System Management Mode and Cache Flushing Regardless of the on-chip cache mode (i.e., write-through or write-back) it is recommended that SMRAM be non-overlaid.
System Management Mode (SMM) Architectures—Intel® Quark Core If SMRAM is overlaid with normal memory space, additional system design features are needed to ensure that cache coherency is maintained. Table 48 lists the cache flushing requirements for entering and exiting the SMM when the SMRAM is overlaid with normal memory space. Table 48.
Intel® Quark Core—System Management Mode (SMM) Architectures 8.6.2.2 Snoop During SMM Snoops cycles are allowed during SMM. However, because the SMRAM is always cached as a write-through, there can never be a snoop hit to a modified line in the SMRAM address space. Consequently, if there is a snoop hit to a modified line, it corresponds to the normal address space.
System Management Mode (SMM) Architectures—Intel® Quark Core least 20 CLK cycles after SMIACT# is de-asserted. Be careful not to block the global system RESET, which may be necessary to recover from a system crash. 2. During execution of the RSM instruction to exit SMM, there is a small time window between the de-assertion of SMIACT# and the completion of the RSM microcode. If SRESET is asserted during this window, it is possible that the SMRAM space will be violated.
Intel® Quark Core—System Management Mode (SMM) Architectures • Due to the Real Mode style of base-address formation, a far jump or call cannot transfer control to a segment with a base address of more than 20 bits (one Mbyte). 8.7.2 Exception Handling Upon entry into SMM, external interrupts that require handlers are disabled (the IF bit in the EFLAGS is cleared). This is necessary because, while the processor is in SMM, it is running in a separate memory space.
Hardware Interface—Intel® Quark Core 9.0 Hardware Interface 9.1 Introduction The Intel® Quark SoC X1000 Core has separate parallel buses for addresses and data. The bidirectional data bus is 32 bits wide. The address bus consists of two components: 30 address lines (A[31:2]) and 4-byte enable lines (BE[3:0]#). The address lines form the upper 30 bits of the address and the byte enables select individual bytes within a 4-byte location.
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Hardware Interface—Intel® Quark Core address space (00000000H through 0000FFFFH). A[31:2] identify addresses to a 4byte location. BE[3:0]# identify which bytes within the 4-byte location are involved in the current transfer. Addresses are driven back into the Intel® Quark SoC X1000 Core over A[31:4] during cache line invalidations. The address lines are active high. When used as inputs into the processor, A[31:4] must meet the setup and hold times t22 and t23.
Intel® Quark Core—Hardware Interface indicated by the byte enable and bus size signals. It is valid only in the clock immediately after read data is returned to the Intel® Quark SoC X1000 Core. At all other times, it is inactive (high). PCHK# is never floated. Driving PCHK# is the only effect that bad input parity has on the Intel® Quark SoC X1000 Core. The Intel® Quark SoC X1000 Core does not vector to a bus error interrupt when bad data parity is returned.
Hardware Interface—Intel® Quark Core 9.2.5.3 Pseudo-Lock Output (PLOCK#) The pseudo-lock feature allows atomic reads and writes of memory operands greater than 32 bits. These operands require more than one cycle to transfer. The Intel® Quark SoC X1000 Core asserts PLOCK# during segment table descriptor reads (64 bits) and cache line fills (128 bits). When PLOCK# is asserted, no other master is given control of the bus between cycles.
Intel® Quark Core—Hardware Interface RDY# is active low, and is not provided with an internal pull-up resistor. This input must satisfy setup and hold times t16 and t17 for proper chip operation. 9.2.7 Burst Control 9.2.7.1 Burst Ready Input (BRDY#) BRDY# performs the same function during a burst cycle that RDY# performs during a non-burst cycle.
Hardware Interface—Intel® Quark Core 9.2.8.2 Soft Reset Input (SRESET) The SRESET (soft reset) input has the same functions as RESET, but does not change the SMBASE, and RESERVED# is not sampled on the falling edge of SRESET. If the system uses SMBASE relocation, the soft resets should be handled using the SRESET input. SRESET should not be used for the cold boot-up power-on reset. The SRESET input pin is provided to save the status of SMBASE during a mode change.
Intel® Quark Core—Hardware Interface 9.2.8.6 Non-maskable Interrupt Request Input (NMI) NMI is the non-maskable interrupt request signal. Asserting NMI causes an interrupt with an internally supplied vector value of 2. External interrupt acknowledge cycles are not generated because the NMI interrupt vector is internally generated. When NMI processing begins, the NMI signal is masked internally until the IRET instruction is executed. NMI is rising edge sensitive after internal synchronization.
Hardware Interface—Intel® Quark Core performing a code fetch, and that cycle is backed off (BOFF#), the Intel® Quark SoC X1000 Core will recognize HOLD before restarting the cycle. The code fetch can be noncacheable or cacheable and non-burst or burst. The BREQ, HLDA, PCHK# and FERR# pins are not floated during bus hold. The Intel® Quark SoC X1000 Core maintains its bus in this state until the HOLD is de-asserted. Refer to Section 10.3.
Intel® Quark Core—Hardware Interface 9.2.10.1 Address Hold Request Input (AHOLD) AHOLD is the address hold request. It allows another bus master access to the Intel® Quark SoC X1000 Core address bus for performing an internal cache invalidation cycle. Asserting AHOLD forces the Intel® Quark SoC X1000 Core to stop driving its address bus in the next clock. While AHOLD is active only the address bus is floated, the remainder of the bus can remain active.
Hardware Interface—Intel® Quark Core FLUSH# also determines whether or not the three-state test mode of the Intel® Quark SoC X1000 Core is invoked on assertion of RESET (see Section B.3, “Intel® Quark SoC X1000 Core JTAG” on page 304). 9.2.12 Page Cacheability (PWT, PCD) The PWT and PCD output signals correspond to two user attribute bits in the page table entry. When paging is enabled, PWT and PCD correspond to bits 3 and 4 of the page table entry, respectively.
Intel® Quark Core—Hardware Interface 1. The stack fault, invalid operation, and denormal exceptions on all transcendental instructions, integer arithmetic instructions, FSQRT, FSCALE, FPREM(1), FXTRACT, FBLD, and FBSTP. 2. Any exceptions on store instructions (including integer store instructions). The following class of floating-point exceptions assert FERR# only after encountering the next floating-point instruction: 1.
Hardware Interface—Intel® Quark Core BS16# and BS8# are active low and are provided with small internal pull-up resistors. BS16# and BS8# must satisfy the setup and hold times t14 and t15 for proper chip operation. 9.2.16 Address Bit 20 Mask (A20M#) Note: The implementation of Intel® Quark Core on Intel® Quark SoC X1000 does not use the A20M# pin; it is tied to 1'b1.
Intel® Quark Core—Hardware Interface Table 50. Differences between CACHE# and PCD (Sheet 2 of 2) Snoop-forced write-back low low S-state write-through high same as PCD(3) I-state write-through (2) high same as PCD(3) Notes: 1. Includes line fills and non-cacheable reads. During locked read cycles CACHE# is inactive. The noncacheable reads may or may not be burst. 2. Due to the non-allocate on write policy, this includes both cacheable and non-cacheable writes.
Hardware Interface—Intel® Quark Core Table 52. HITM# vs. Other Intel® Quark Core Signals Pin Symbol EADS# 9.2.17.4 Relation To This Signal HITM# is asserted due to an EADS#-driven snoop, provided the snooped line is in the M-state in the cache. HLDA, BOFF# HITM# does not float under these signals. ADS#, CACHE# The beginning of a snoop write-back cycle is identified by the assertion of ADS#, CACHE#, and HITM#.
Intel® Quark Core—Hardware Interface 9.2.17.6 Write-Back/Write-Through (WB/WT#) WB/WT# enables Enhanced Bus mode (write-back cache). It also allows the system to define a cached line as write-through or write-back. WB/WT# is sampled at the falling edge of RESET to determine if Enhanced Bus mode is enabled (WB/WT# must be driven for two clocks before and two clocks after RESET to be recognized by the processor).
Hardware Interface—Intel® Quark Core In addition to using TCK as a free running clock, it may be stopped in a low, O, state, indefinitely as described in IEEE 1149.1. While TCK is stopped in the low state, the JTAG latches retain their state. TCK is a clock signal and is used as a reference for sampling other JTAG signals. On the rising edge of TCK, TMS and TDI are sampled. On the falling edge of TCK, TDO is driven. 9.2.18.
Intel® Quark Core—Hardware Interface 9.3.1 Interrupt Logic The Intel® Quark SoC X1000 Core contains a two-clock synchronizer on the interrupt line. An interrupt request reaches the internal instruction execution unit two clocks after the INTR pin is asserted if proper setup is provided to the first stage of the synchronizer. There is no special logic in the interrupt path other than the synchronizer.
Hardware Interface—Intel® Quark Core The SMI# input must be held inactive for at least four clocks after it is asserted to reset the edge triggered logic. A subsequent SMI# might not be recognized if the SMI# input is not held inactive for at least four clocks after being asserted. SMI#, like NMI, is not affected by the IF bit in the EFLAGS register and is recognized on an instruction boundary. An SMI# does not break locked bus cycles. SMI# has a higher priority than NMI and is not masked during an NMI.
Intel® Quark Core—Hardware Interface Writes are driven onto the external bus in the same order in which they are received by the write buffers. Under certain conditions, a memory read can go onto the external bus before the memory writes pending in the buffer, even though the writes occurred earlier in the program execution. A memory read is reordered in front of all writes in the buffers only under the following conditions: If all writes pending in the buffers are cache hits and the read is a cache miss.
Hardware Interface—Intel® Quark Core 9.4.1 Write Buffers and I/O Cycles Input/Output (I/O) cycles must be handled in a different manner by the write buffers. I/O reads are never reordered in front of buffered memory writes. This ensures that the Intel® Quark SoC X1000 Core updates all memory locations before reading status from an I/O device. The Intel® Quark SoC X1000 Core never buffers single I/O writes.
Intel® Quark Core—Hardware Interface 9.5.1 Floating-Point Register Values In addition to the register values listed above, Intel® Quark SoC X1000 Core has the floating-point register values shown in Table 57. If the BIST is performed, the floating-point registers are initialized as if the FINIT/FNINIT (initialize processor) instruction were executed. If the BIST is not executed, the floating-point registers are unchanged.
Hardware Interface—Intel® Quark Core Table 56. Floating-Point Values after Reset (Sheet 2 of 2) FEA Unchanged FCS 0000h Unchanged FDS 0000h Unchanged FOP 000h Unchanged Undefined Unchanged FSTACK 9.5.2 00000000h Pin State During Reset The Intel® Quark SoC X1000 Core recognizes and can respond to HOLD, AHOLD, and BOFF# requests regardless of the state of RESET. Thus, even though the processor is in reset, it can float its bus in response to any of these requests.
Intel® Quark Core—Hardware Interface Figure 72. Pin States During RESET TX TX TX TX TI TI TI TI (8) CLK At least 15 CLK periods RESET ~217CLK if no self-test (1) (1) ~220 CLK if no self-test T20 T20 AHOLD INPUTS (6) (4) FLUSH# Sync) FLUSH# (Async) (5) A20M# (Sync) (2) A20M# (Async) (3) ADS# A31:4, MIO#, BLAST UNDEFINED A3, A2, PLOCK UNDEFINED OUTPUTS BREQ D/C#, W/R#, PCHK# LOCK# D[31:0] HLDA (7) SMIACT# WB/WT# CACHE# HITM# (9) (10) See notes on next page.
Hardware Interface—Intel® Quark Core Notes to Figure 72: 1. RESET is an asynchronous input. t20 must be met only to guarantee recognition on a specific clock edge. 2. When A20M# is driven synchronously, it must be driven high (inactive) for the CLK edge prior to the falling edge of RESET to ensure proper operation. A20M# setup and hold times must be met. Intel® Quark Core on Intel® Quark SoC X1000 does not use the A20M# pin; it is tied to 1'b1. 3.
Intel® Quark Core—Hardware Interface 7:0 depend on whether or not BIST is performed. Table 57 shows the state of FERR# signal after reset and before the execution of the FINIT/FNINIT instruction. Table 57.
Hardware Interface—Intel® Quark Core M/IO# = 0, D/C# = 0, W/R# = 1, address bus = 0000 0010H (A4 = 1), BE3:0# = 1011, data bus = undefined The latency between a STPCLK# request and the Stop Grant bus cycle depends on the current instruction, the amount of data in the processor write buffers, and the system memory performance (see Figure 73). Figure 73. Stop Clock Protocol CLK STPCLK# TSU THD Stop Grant Bus Cycle ADDR RDY# 9.6.
Intel® Quark Core—Hardware Interface Table 58. 9.6.
Hardware Interface—Intel® Quark Core Table 59. Write-Back Enhanced Intel® Quark SoC X1000 Core Pin States during Stop Grant Bus Cycle (Sheet 2 of 2) Signal Type State BLAST# O Previous state FERR# O Previous state PCHK# O Previous state PWT, PCD O Previous state CACHE# O Inactive(1) (high) HITM# O Inactive(1) (high) SMIACT# O Previous state Notes: 1.
Intel® Quark Core—Hardware Interface are not recognized until one CLK after STPCLK# is de-asserted (see Figure 75). While in the Stop Grant state, the processor does not recognize transitions on the interrupt signals (SMI#, NMI, and INTR). Driving an active edge on either SMI# or NMI does not guarantee recognition and service of the interrupt request following exit from the Stop Grant state.
Hardware Interface—Intel® Quark Core 9.6.4.3 Stop Clock State Stop Clock state is entered from the Stop Grant state by stopping the CLK input (either logic high or logic low). None of the processor input signals should change state while the CLK input is stopped. Any transition on an input signal (with the exception of INTR, NMI and SMI#) before the processor has returned to the Stop Grant state results in unpredictable behavior.
Intel® Quark Core—Hardware Interface A FLUSH# event during the Stop Grant state or the Auto HALT Power Down state is latched and acted upon by asserting the internal FLUSH# signal for one clock upon reentering the Normal state. 9.6.4.6 Auto Idle Power Down State When the processor is known to be truly idle and waiting for RDY# or BRDY# from a memory or I/O bus cycle read, the Intel® Quark SoC X1000 Core reduces its core clock rate to equal that of the external CLK frequency without affecting performance.
Hardware Interface—Intel® Quark Core Figure 76. Write-Back Enhanced Intel® Quark SoC X1000 Core Stop Clock State Machine (Enhanced Bus Configuration) 4. Auto HALT Power Down State 1. Normal State HALT CLK Running Halt Bus Cycle Generated ICC approximately 100 µA INTR, NMI, SMI#, RESET, SRESET Reset Normal Execution All Clocks Running STPCLK# asserted STPCLK# asserted and Stop Grant bus cycles generated STPCLK# de-asserted EADS# STPCLK# asserted 5.
Intel® Quark Core—Hardware Interface • The processor latches and responds to the inputs BOFF#, EADS#, AHOLD, and HOLD. The processor does not recognize any other inputs while in the Stop Grant state except FLUSH#. Other input signals to the processor are not recognized until the CLK following the CLK in which STPCLK# is de-asserted (see Figure 76). • The processor generates a Stop Grant bus cycle only when entering that state from the Normal or the Auto HALT Power Down state.
Hardware Interface—Intel® Quark Core in this state, the FLUSH# is serviced by transitioning to the Stop Clock Flush state. After the FLUSH# is completed, the processor returns to the Auto HALT Power Down state. The system can generate a STPCLK# while the processor is in the Auto HALT Power Down state. The processor then generates a Stop Grant bus cycle and enters the Stop Grant state from the Auto HALT Power Down state.
Intel® Quark Core—Bus Operation 10.0 Bus Operation When the internal cache of the Write-Back Enhanced Intel® Quark SoC X1000 Core is configured in write-through mode, the processor bus operates in Standard Bus mode. However, when the internal cache of the Write-Back Enhanced Intel® Quark SoC X1000 Core is configured in write-back mode, the bus then operates in the Enhanced Bus mode, which is described in Section 10.4. 10.
Bus Operation—Intel® Quark Core Table 61. Generating A[31:0] from BE[3:0]# and A[31:A2] Intel® Quark SoC X1000 Core Address Signals Physical Address Figure 77. BE3# BE2# BE1# BE0# A31 ... A2 A1 A0 A31 ... A2 0 0 X X X 0 A31 ... A2 0 1 X X 0 1 A31 ... A2 1 0 X 0 1 1 A31 ... A2 1 1 0 1 1 1 Physical Memory and I/O Spaces FFFFFFFFH Not Accessible Physical Memory 4 Gbyte Not Accessible 00000000H Physical Memory Space 10.1.1.
Intel® Quark Core—Bus Operation Figure 78. Physical Memory and I/O Space Organization 32-Bit Wide Organization FFFFFFFFH FFFFFFFCH { { { { 00000003H BE3# BE2# BE1# 00000000H BE0# 16-Bit Wide Organization FFFFFFFEH 00000001H 00000000H { { FFFFFFFFH BHE# BLE# 16-bit memories are organized as arrays of two bytes each. Each two bytes begins at addresses divisible by two. The byte enables BE[3:0]#, must be decoded to A1, BLE# and BHE# to address 16-bit memories.
Bus Operation—Intel® Quark Core The external system must contain buffers to enable the Intel® Quark SoC X1000 Core to read and write data on the appropriate data bus pins. Table 63 shows the data bus lines to which the Intel® Quark SoC X1000 Core expects data to be returned for each valid combination of byte enables and bus sizing options. Table 62.
Intel® Quark Core—Bus Operation In 32-bit physical memories, such as the one shown in Figure 79, each 4-byte word begins at a byte address that is a multiple of four. A[31:2] are used as a 4-byte word select. BE[3:0]# select individual bytes within the 4-byte word. BS8# and BS16# are deasserted for all bus cycles involving the 32-bit array. For 16- and 8-bit memories, byte swapping logic is required for routing data to the appropriate data lines and logic is required for generating BHE#, BLE# and A1.
Bus Operation—Intel® Quark Core Table 64.
Intel® Quark Core—Bus Operation Figure 81. Logic to Generate A1, BHE# and BLE# for 16-Bit Buses Combinations of BE[3:0]# that never occur are those in which two or three asserted byte enables are separated by one or more deasserted byte enables. These combinations are “don't care” conditions in the decoder. A decoder can use the nonoccurring BE[3:0]# combinations to its best advantage. Figure 82 shows a Intel® Quark SoC X1000 Core data bus interface to 16- and 8-bit wide memories.
Bus Operation—Intel® Quark Core Figure 82. Data Bus Interface to 16- and 8-Bit Memories Intel® Quark Core D[7:0] 8 D[15:8] D[23:16] D[31:24] 8 8 8 32-Bit Memory BS8# BS16# (A[31:2], BE[3:0]#) Address Decode 10.1.4 Byte Swap Logic 16 Byte Swap Logic 8 16-Bit Memory 8-Bit Memory Dynamic Bus Sizing during Cache Line Files BS8# and BS16# can be driven during cache line fills. The Intel® Quark SoC X1000 Core generates enough 8- or 16-bit cycles to fill the cache line.
Intel® Quark Core—Bus Operation Table 65. Generating A0, A1 and BHE# from the Intel® Quark SoC X1000 Core Byte Enables (Sheet 2 of 2) First Cache Fill Cycle BE3# BE2# BE1# Any Other Cycle BE0# A0 A1 BHE# A0 A1 BHE# †0 0 1 1 0 0 0 0 1 0 †0 1 1 1 0 0 0 1 1 0 KEY: † =a non-occurring pattern of Byte Enables; either none are asserted or the pattern has byte enables asserted for non-contiguous bytes 10.1.
Bus Operation—Intel® Quark Core In the unaligned transfer described above, the processor requested three bytes on the first cycle. When the external system asserts BS16# during this 3-byte transfer, the lower word is transferred first followed by the upper byte. In the final cycle, the lower byte of the 4-byte operand is transferred, as shown in the 32-bit example above. 10.2 Bus Arbitration Logic Bus arbitration logic is needed with multiple bus masters.
Intel® Quark Core—Bus Operation Figure 84. Single Intel® Quark Core with DMA Intel® Quark Core DMA Address Bus Data Bus Control Bus I/O MEM Figure 85 shows more than one primary bus master and two secondary masters, and the arbitration logic is more complex. The arbitration logic resolves bus contention by ensuring that all device requests are serviced one at a time using either a fixed or a rotating scheme.
Bus Operation—Intel® Quark Core Figure 85. Single Intel® Quark Core with Multiple Secondary Masters BREQ BDCK ACK HLDA 0 HOLD 0 Arbitration Logic ACQ DRQ Intel® Quark Core DMA DACK Address Bus Data Bus Control Bus I/O MEM As systems become more complex and include multiple bus masters, hardware must be added to arbitrate and assign the management of bus time to each master.
Intel® Quark Core—Bus Operation The Intel® Quark SoC X1000 Core asserts BREQ when it requires control of the bus. BREQ notifies the arbitration logic that the processor has pending bus activity and requests the bus. When its HOLD input is inactive and its HLDA signal is deasserted, the Intel® Quark SoC X1000 Core can acquire the bus. Otherwise if HOLD is asserted, then the Intel® Quark SoC X1000 Core has to wait for HOLD to be deasserted before acquiring the bus.
Bus Operation—Intel® Quark Core Figure 86. Basic 2-2 Bus Cycle Ti T1 T2 T1 T2 T1 T2 T1 T2 Ti CLK ADS# A31–A2 M/IO# D/C# BE3#–BE0# W/R# RDY# BLAST# † ‡ † DATA ‡ PCHK# Read Write Read Write † To Processor ‡ From Processor 242202-031 The non-burst ready input (RDY#) is asserted by the external system in the second clock.
Intel® Quark Core—Bus Operation Figure 87. Basic 3-3 Bus Cycle Ti T1 T2 T2 T1 T2 T2 Ti CLK ADS# A31–A2 M/IO# D/C# BE3#–BE0# W/R# RDY# BLAST# ‡ † DATA Read † ‡ Write To Processor From Processor 242202-032 The burst ready input (BRDY#) must be deasserted on all clock edges where RDY# is deasserted for proper operation of these simple non-burst cycles. 10.3.
Bus Operation—Intel® Quark Core Burst cycles begin with the Intel® Quark SoC X1000 Core driving out an address and asserting ADS# in the same manner as non-burst cycles. The Intel® Quark SoC X1000 Core indicates that it is willing to perform a burst cycle by holding the burst last signal (BLAST#) deasserted in the second clock of the cycle. The external system indicates its willingness to do a burst cycle by asserting the burst ready signal (BRDY#).
Intel® Quark Core—Bus Operation 10.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers Figure 88 illustrates a two-cycle, non-burst, non-cacheable read. This transfer is simply a sequence of two single cycle transfers. The Intel® Quark SoC X1000 Core indicates to the external system that this is a multiple cycle transfer by deasserting BLAST# during the second clock of the first cycle. The external system asserts RDY# to indicate that it will not burst the data.
Bus Operation—Intel® Quark Core Figure 89. Non-Cacheable Burst Cycle Ti T1 T2 T1 T2 Ti CLK ADS# A31–A2 M/IO# D/C# W/R# BE3#–BE0# RDY# BRDY# KEN# BLAST# † DATA † † To Processor 10.3.3 242202-034 Cacheable Cycles Any memory read can become a cache fill operation. The external memory system can allow a read request to fill a cache line by asserting KEN# one clock before RDY# or BRDY# during the first cycle of the transfer on the external bus.
Intel® Quark Core—Bus Operation conditions 1–3 in the above list. In addition, the Intel® Quark SoC X1000 Core drives PCD high whenever the CD bit in CR0 is set, so that external hardware can evaluate condition 4. Cacheable cycles can be burst or non-burst. 10.3.3.1 Byte Enables during a Cache Line Fill For the first cycle in the line fill, the state of the byte enables should be ignored. In a non-cacheable memory read, the byte enables indicate the bytes actually required by the memory or code fetch.
Bus Operation—Intel® Quark Core Figure 90. Non-Burst, Cacheable Cycles Ti T1 T2 T1 T2 T1 T2 T1 T2 Ti CLK ADS# A31–A2 M/IO# D/C# W/R# BE3#–BE0# RDY# BRDY# KEN# BLAST# DATA † † † † † To Processor 242202-035 10.3.3.3 Burst Cacheable Cycles Figure 91 illustrates a burst mode cache fill. As in Figure 90, the transfer becomes a cache line fill when the external system asserts KEN# at the end of the first clock in the cycle.
Intel® Quark Core—Bus Operation Figure 91. Burst Cacheable Cycle Ti T1 T2 T2 T2 T2 Ti CLK ADS# A31–A4 M/IO# D/C# W/R# A3–A2 BE3#–BE0# RDY# BRDY# KEN# BLAST# † DATA † † † PCHK# † To Processor 242202-036 10.3.3.4 Effect of Changing KEN# during a Cache Line Fill KEN# can change multiple times as long as it arrives at its final value in the clock before RDY# or BRDY# is asserted. This is illustrated in Figure 92. Note that the timing of BLAST# follows that of KEN# by one clock.
Bus Operation—Intel® Quark Core Figure 92. Effect of Changing KEN# Ti T1 T2 T2 T2 T1 T2 T2 CLK ADS# A31–A2 M/IO# D/C# W/R# A3–A2 BE3#–BE0# RDY# KEN# BLAST# † DATA † † To Processor 242202-037 10.3.4 Burst Mode Details 10.3.4.1 Adding Wait States to Burst Cycles Burst cycles need not return data on every clock. The Intel® Quark SoC X1000 Core strobes data into the chip only when either RDY# or BRDY# is asserted. Deasserting BRDY# and RDY# adds a wait state to the transfer.
Intel® Quark Core—Bus Operation Figure 93. Slow Burst Cycle Ti T1 T2 T2 T2 T2 T2 T2 T2 T2 CLK ADS# A31–A2 M/IO# D/C# W/R# A3–A2 BE3#–BE0# RDY# BRDY# KEN# BLAST# † † DATA † † † To Processor 242202-038 10.3.4.2 Burst and Cache Line Fill Order The burst order used by the Intel® Quark SoC X1000 Core is shown in Table 67. This burst order is followed by any burst cycle (cache or not), cache line fill (burst or not) or code prefetch.
Bus Operation—Intel® Quark Core Figure 94. Burst Cycle Showing Order of Addresses Ti T1 T2 T2 T2 T2 Ti CLK ADS# A31–A2 104 100 10C 108 RDY# BRDY# KEN# BLAST# † DATA † † † † To Processor 242202-039 The sequences shown in Table 67 accommodate systems with 64-bit buses as well as systems with 32-bit data buses. The sequence applies to all bursts, regardless of whether the purpose of the burst is to fill a cache line, perform a 64-bit read, or perform a pre-fetch.
Intel® Quark Core—Bus Operation Figure 95. Interrupted Burst Cycle Ti T1 T2 T2 T1 T2 Ti T2 CLK ADS# A31–A2 104 100 10C 108 RDY# BRDY# KEN# BLAST# † DATA † † † † To Processor 242202-067 KEN# need not be asserted in the first data cycle of the second part of the transfer shown in Figure 96. The cycle had been converted to a cache fill in the first part of the transfer and the Intel® Quark SoC X1000 Core expects the cache fill to be completed.
Bus Operation—Intel® Quark Core Figure 96. Interrupted Burst Cycle with Non-Obvious Order of Addresses Ti T1 T2 T1 T2 T2 Ti T2 CLK ADS# A31–A2 104 100 10C 108 RDY# BRDY# KEN# BLAST# † DATA † † † † To Processor 242202-068 10.3.5 8- and 16-Bit Cycles The Intel® Quark SoC X1000 Core supports both 16- and 8-bit external buses through the BS16# and BS8# inputs.
Intel® Quark Core—Bus Operation Figure 97. 8-Bit Bus Size Cycle Ti T1 T1 T2 T2 T1 T2 Ti CLK ADS# A31–A2 M/IO# D/C# W/R# BE3#–BE0# RDY# BS8# BLAST# † DATA † † † To Processor 242202-069 Extra cycles forced by BS16# and BS8# signals should be viewed as independent bus cycles. BS16# and BS8# should be asserted for each additional cycle unless the addressed device can change the number of bytes it can return between cycles.
Bus Operation—Intel® Quark Core Figure 98. Burst Write as a Result of BS8# or BS16# Ti T1 T2 T2 T2 T2 Ti CLK ADS# ADDR SPEC BE3#–BE0# RDY# BRDY# BS8# BLAST# DATA ‡ ‡ From Processor 242202–143 10.3.6 Locked Cycles Locked cycles are generated in software for any instruction that performs a readmodify-write operation.
Intel® Quark Core—Bus Operation Figure 99. Locked Bus Cycle Ti T1 T2 T1 T2 Ti CLK ADS# A31–A2 M/IO# D/C# BE3#–BE0# W/R# RDY# † DATA ‡ LOCK# Read Write † To Processor ‡ From Processor 242202-080 10.3.7 Pseudo-Locked Cycles Pseudo-locked cycles assure that no other master is given control of the bus during operand transfers that take more than one bus cycle. For the Intel® Quark SoC X1000 Core, examples include 64-bit description loads and cache line fills.
Bus Operation—Intel® Quark Core PLOCK# can change several times during a cycle, settling to its final value in the clock in which RDY# is asserted. 10.3.7.1 Floating-Point Read and Write Cycles For Intel® Quark SoC X1000 Core, 64-bit floating-point read and write cycles are also examples of operand transfers that take more than one bus cycle. Figure 100.
Intel® Quark Core—Bus Operation Figure 101. Fast Internal Cache Invalidation Cycle Ti T1 Ti T2 Ti T1 T2 Ti CLK ADS# ADDR † AHOLD EADS# RDY# DATA † † BREQ † To Processor 242202-091 Figure 102.
Bus Operation—Intel® Quark Core 10.3.8.1 Rate of Invalidate Cycles The Intel® Quark SoC X1000 Core can accept one invalidate per clock except in the last clock of a line fill. One invalidate per clock is possible as long as EADS# is deasserted in ONE or BOTH of the following cases: 1. In the clock in which RDY# or BRDY# is asserted for the last time. 2. In the clock following the clock in which RDY# or BRDY# is asserted for the last time. This definition allows two system designs.
Intel® Quark Core—Bus Operation Figure 103. System with Second-Level Cache Intel® Quark Core Address, Data and Control Bus Second-Level Cache Address, Data and Control Bus System Bus External Memory External Bus Master If the system asserts EADS# before the first data in the line fill is returned to the Intel® Quark SoC X1000 Core, the system must return data consistent with the new data in the external memory upon resumption of the line fill after the invalidation cycle.
Bus Operation—Intel® Quark Core Figure 104. Cache Invalidation Cycle Concurrent with Line Fill Ti T1 T2 T2 T2 T2 T2 T2 Ti CLK ADS# † ADDR † AHOLD 1 2 EADS# RDY# BRDY# KEN# † DATA † † † † To Processor NOTES: 1. Data returned must be consistent if its address equals the invalidation address in this clock. 2. Data returned is not cached if its address equals the invalidation address in this clock. 10.3.
Intel® Quark Core—Bus Operation Figure 105. HOLD/HLDA Cycles Ti Ti T1 T2 Ti Ti T1 CLK ADS# A31–A2 M/IO# D/C# W/R# BE3#–BE0# RDY# ‡ DATA HOLD HLDA ‡ From Processor 242202-146 Note that HOLD is recognized during un-aligned writes (less than or equal to 32 bits) with BLAST# being asserted for each write. For a write greater than 32-bits or an unaligned write, HOLD# recognition is prevented by PLOCK# getting asserted.
Bus Operation—Intel® Quark Core Figure 106. HOLD Request Acknowledged during BOFF# Ti Ti Ti Ti Ti T1 T2 Ti Ti Ti Ti CLK ADS# M/IO# D/C# W/R# KEN# BRDY# RDY# HOLD HLDA BOFF# 242202-095 10.3.10 Interrupt Acknowledge The Intel® Quark SoC X1000 Core generates interrupt acknowledge cycles in response to maskable interrupt requests that are generated on the interrupt request input (INTR) pin. Interrupt acknowledge cycles have a unique cycle type generated on the cycle type pins.
Intel® Quark Core—Bus Operation Figure 107. Interrupt Acknowledge Cycles Ti T1 T2 Ti Ti T1 T2 Ti CLK 4 Clocks ADS# 04 ADDR 00 RDY# † DATA LOCK# † To Processor 242202-096 10.3.11 Special Bus Cycles The Intel® Quark SoC X1000 Core provides special bus cycles to indicate that certain instructions have been executed, or certain conditions have occurred internally. The special bus cycles are identified by the status of the pins shown in Table 68.
Bus Operation—Intel® Quark Core 10.3.11.2 Shutdown Indication Cycle The Intel® Quark SoC X1000 Core shuts down as a result of a protection fault while attempting to process a double fault. A shutdown indication cycle is performed to indicate that the processor has entered a shutdown state. The shutdown indication cycle is identified by the bus definition signals in special bus cycle state and a byte address of 0. 10.3.11.
Intel® Quark Core—Bus Operation 10.3.12 Bus Cycle Restart In a multi-master system, another bus master may require the use of the bus to enable the Intel® Quark SoC X1000 Core to complete its current bus request. In this situation, the Intel® Quark SoC X1000 Core must restart its bus cycle after the other bus master has completed its bus transaction. A bus cycle may be restarted if the external system asserts the backoff (BOFF#) input.
Bus Operation—Intel® Quark Core Figure 110. Restarted Write Cycle Ti T1 Tb T2 Tb T1b T2 Ti CLK ADS# ADDR SPEC 100 100 RDY# BRDY# BOFF# ‡ DATA ‡ ‡ From Processor 242202-147 The device asserting BOFF# is free to run cycles while the Intel® Quark SoC X1000 Core bus is in its high impedance state. If backoff is requested after the Intel® Quark SoC X1000 Core has started a cycle, the new master should wait for memory to assert RDY# or BRDY# before assuming control of the bus.
Intel® Quark Core—Bus Operation 10.3.13 Bus States A bus state diagram is shown in Figure 111. A description of the signals used in the diagram is given in Table 69. Figure 111.
Bus Operation—Intel® Quark Core 10.3.14 Floating-Point Error Handling for the Intel® Quark SoC X1000 Core The Intel® Quark SoC X1000 Core provides two options for reporting floating-point errors. The simplest method is to raise interrupt 16 whenever an unmasked floatingpoint error occurs. This option may be enabled by setting the NE bit in control register 0 (CR0). The Intel® Quark SoC X1000 Core also provides the option of allowing external hardware to determine how floating-point errors are reported.
Intel® Quark Core—Bus Operation In systems with user-defined error reporting, the FERR# pin is connected to the interrupt controller. When an unmasked floating-point error occurs, an interrupt is raised. If IGNNE# is high at the time of this interrupt, the Intel® Quark SoC X1000 Core freezes (disallowing execution of a subsequent floating-point instruction) until the interrupt handler is invoked.
Bus Operation—Intel® Quark Core 2. Four signals: INV, WB/WT#, HITM#, and CACHE#, support the write-back operation of the internal cache. 3. The SRESET signal does not write back, invalidate, or disable the cache. Special test modes are also not initiated through SRESET. 4. The FLUSH# signal behaves the same as the WBINVD instruction. Upon assertion, FLUSH# writes back all modified lines, invalidates the cache, and issues two special bus cycles. 5. The PLOCK# signal remains deasserted. 10.4.
Intel® Quark Core—Bus Operation cacheable by either CACHE# or KEN#. In this case, BLAST# is also high in the same cycle as the first BRDY# (in clock four). To improve performance, the memory controller should try to complete the cycle as a burst cycle. The assertion of CACHE# on a write cycle signifies a replacement or snoop write-back cycle. These cycles consist of four doubleword transfers (either bursts or non-burst).
Bus Operation—Intel® Quark Core X1000 Core invalidates the line if the system snoop hits an S-state, E-state, or M-state line, provided INV was driven high during snooping. If INV is driven low during a snoop cycle, a modified line is written back to memory and remains in the cache as a writeback line; a write-through line also remains in the cache as a write-through line.
Intel® Quark Core—Bus Operation Table 71. Various Scenarios of a Snoop Write-Back Cycle Colliding with an On-Going Cache Fill or Replacement Cycle Snoop to a Different Line than the Line Being Filled Snoop to the Line That Is Being Replaced Snoop to a Different Line than the Line Being Replaced AHOLD Read all line fill data into cache line buffer. Update cache only if snoop occurred with INV = 0 No write-back cycle because the line has not been modified yet. Complete fill if the cycle is burst.
Bus Operation—Intel® Quark Core Figure 113. Snoop Cycle Invalidating a Modified Line 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK AHOLD EADS# INV HITM# A31–A4 * A3–A2 ** 0 4 8 C ADS# BLAST# CACHE# BRDY# W/R# * ** To Processor Write-back from Processor 242202-150 The next ADS# for a new cycle can occur immediately after the last RDY# or BRDY# of the write-back cycle.
Intel® Quark Core—Bus Operation In Figure 114, the snoop to an M-state line causes a snoop write-back cycle. The WriteBack Enhanced Intel® Quark SoC X1000 Core asserts HITM# two clocks after the EADS#, but delays the snoop write-back cycle until the line fill is completed, because the line fill shown in Figure 114 is a burst cycle. In this figure, AHOLD is asserted one clock after ADS#.
Bus Operation—Intel® Quark Core 10.4.3.2.2 AHOLD Snoop Overlaying a Non-Burst Cycle When AHOLD overlays a non-burst cycle, snooping is based on the completion of the current non-burst transfer (ADS#-RDY# transfer). Figure 115 shows a snoop cycle under AHOLD overlaying a non-burst line-fill cycle. HITM# is asserted two clocks after EADS#, and the non-burst cycle is fractured after the RDY# for a specific single transfer is asserted.
Intel® Quark Core—Bus Operation 3. If the snoop occurs when INV = “1”, the processor never updates the cache with the fill data. 4. If the snoop occurs when INV = “0”, the processor loads the line into the internal cache. 10.4.3.3 Snoop During Replacement Write-Back If the cache contains valid data during a line fill, one of the cache lines may be replaced as determined by the Least Recently Used (LRU) algorithm. Refer to Chapter 7.0, “OnChip Cache” for a detailed discussion of the LRU algorithm.
Bus Operation—Intel® Quark Core If there is a snoop hit to a different line from the line being replaced, and if the replacement write-back cycle is burst, the replacement cycle goes to completion. Only then is the snoop write-back cycle initiated. If the replacement write-back cycle is a non-burst cycle, and if there is a snoop hit to the same line as the line being replaced, it fractures the replacement write-back cycle after RDY# is asserted for the current non-burst transfer.
Intel® Quark Core—Bus Operation Figure 117. Snoop under BOFF# during a Cache Line-Fill Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK BOFF# EADS# INV HITM# A31–A4 A3–A2 † Linefill 4 0 Write Back Cycle 0 4 C 8 Line Fill Cycle Cont. 0 C 8 ADS# BLAST# CACHE# RDY# BRDY# W/R# † To Processor 242202-154 An ADS# is always issued when a cycle resumes after being fractured by BOFF#.
Bus Operation—Intel® Quark Core 10.4.3.4.2 Snoop under BOFF# during Replacement Write-Back If the system snoop under BOFF# hits the line that is currently being replaced (burst or non-burst), the entire line is written back as a snoop write-back line, and the replacement write-back cycle is not continued. However, if the system snoop hits a different line than the one currently being replaced, the replacement write-back cycle continues after the snoop write-back cycle has been completed.
Intel® Quark Core—Bus Operation 10.4.3.5.1 Snoop under HOLD during Cache Line Fill As shown in Figure 119, HOLD (asserted in clock two) does not fracture the burst cache line-fill cycle until the line fill is completed (in clock five). Upon completing the line fill in clock five, the Write-Back Enhanced Intel® Quark SoC X1000 Core asserts HLDA and the system begins snooping by driving EADS# and INV in the following clock period.
Bus Operation—Intel® Quark Core Figure 120. Snoop using HOLD during a Non-Cacheable, Non-Burstable Code Prefetch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK HOLD HLDA EADS# INV HITM# A3–A2 † Prefetch Cycle A31–A4 0 4 8 Prefetch Cont. Write Back Cycle 0 4 8 C C ADS# BLAST# CACHE# RDY# BRDY# W/R# † To Processor 242202-157 10.4.3.
Intel® Quark Core—Bus Operation to the system that the processor is performing this sequence of cycles, and that the processor should be allowed atomic access for the location accessed during the first locked cycle. A locked operation is a combination of one or more read cycles followed by one or more write cycles with the LOCK# pin asserted. Before a locked read cycle is run, the processor first determines if the corresponding line is in the cache.
Bus Operation—Intel® Quark Core 10.4.4.1 Snoop/Lock Collision If there is a snoop cycle overlaying a locked cycle, the snoop write-back cycle fractures the locked cycle. As shown in Figure 122, after the read portion of the locked cycle is completed, the snoop write-back starts under HITM#. After the write-back is completed, the locked cycle continues. But during all this time (including the write-back cycle), the LOCK# signal remains asserted.
Intel® Quark Core—Bus Operation If the processor is in Standard Bus mode, the processor does not issue special acknowledge cycles in response to the FLUSH# input, although the internal cache is invalidated. The invalidation of the cache in this case, takes only two bus clocks. Figure 123. Flush Cycle T1 T1 T2 T2 T2 T2 T1 T1 T2 T1 T2 T1 T1 CLK ADS# RDY# BRDY# FLUSH# ADDR M/IO# D/C# W/R#, BE3–0# CACHE# Write-Back 1st Flush Acknowledge 2nd Flush Acknowledge BLAST# DATA 242202-160 10.4.
Bus Operation—Intel® Quark Core Figure 124. Snoop under AHOLD Overlaying Pseudo-Locked Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK AHOLD EADS# INV HITM# A31–A4 A3–A2 † Write Back Cycle 0 4 8 C ADS# BLAST# CACHE# PLOCK# W/R# BRDY# † To Processor 242202-161 10.4.6.2 Snoop under HOLD during Pseudo-Locked Cycles As shown in Figure 125, HOLD does not fracture the 64-bit burst transfer.
Intel® Quark Core—Bus Operation Figure 125. Snoop under HOLD Overlaying Pseudo-Locked Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK HOLD HLDA EADS# INV HITM# A31–A4 64-Bit Read Cycle † Write Back Cycle 0 A3–A2 4 8 C ADS# BLAST# CACHE# PLOCK# BRDY# W/R# † To Processor 242202-162 10.4.6.3 Snoop under BOFF# Overlaying a Pseudo-Locked Cycle BOFF# is capable of fracturing any bus operation.
Bus Operation—Intel® Quark Core Figure 126.
Intel® Quark Core—Debugging Support 11.0 Debugging Support The Intel® Quark SoC X1000 Core provides several features that simplify the debugging process. The three categories of on-chip debugging aids are: 1. Code execution breakpoint opcode (0CCH) 2. Single-step capability provided by the TF bit in the Flag register 3. Code and data breakpoint capability provided by the Debug Registers DR[3:0], DR6, and DR7 11.
Debugging Support—Intel® Quark Core 11.3.1 Linear Address Breakpoint Registers (DR[3:0]) Up to four breakpoint addresses can be specified by writing to Debug Registers DR[3:0], shown in Figure 72. The breakpoint addresses specified are 32-bit linear addresses.
Intel® Quark Core—Debugging Support RWi (memory access qualifier bits) A 2-bit RW field exists for each of the four breakpoints. The 2-bit RW field specifies the type of usage that must occur to activate the associated breakpoint. Table 73. LENi Encoding LENi Encoding Breakpoint Field Width Usage of Least Significant Bits in Breakpoint Address Register i, (i=0-3) 00 1 byte All 32-bits used to specify a single-byte breakpoint field.
Debugging Support—Intel® Quark Core Note that instruction execution breakpoints are taken as faults (i.e., before the instruction executes), but data breakpoints are taken as traps (i.e., after the data transfer takes place). Using LENi and RWi to Set Data Breakpoint i A data breakpoint can be set up by writing the linear address into DRi (i = 0–3). For data breakpoints, RWi can equal 01 (write-only) or 11 (write/read). LEN can equal 00, 01, or 11.
Intel® Quark Core—Debugging Support Gi and Li (breakpoint enable, global and local) When either Gi or Li is set, then the associated breakpoint (as defined by the linear address in DRi, the length in LENi and the usage criteria in RWi) is enabled. When either Gi or Li is set, and the Intel® Quark SoC X1000 Core detects the ith breakpoint condition, the exception 1 handler is invoked. When the Intel® Quark SoC X1000 Core performs a task switch to a new Task State Segment (TSS), all Li bits are cleared.
Debugging Support—Intel® Quark Core BD (debug fault due to attempted register access when GD bit set) This bit is set when the exception 1 handler is invoked due to an instruction that attempts to read or write to the debug registers when the GD bit was set. If such an event occurs, then the GD bit is automatically cleared when the exception 1 handler is invoked, allowing the handler access to the debug registers.
Intel® Quark Core—Instruction Set Summary 12.0 Instruction Set Summary This chapter describes the entire encoding structure and provides definitions of all fields occurring within the Intel® Quark SoC X1000 Core instructions. Section 12.2.5, “Intel® Quark SoC X1000 Core Instructions” on page 263 provides product-specific details. • Detailed information on the CPUID instructions can be found in Appendix C, “Feature Determination.” 12.
Instruction Set Summary—Intel® Quark Core 12.1.1 Floating-Point Instructions In addition to the instructions listed above, the Intel® Quark SoC X1000 Core has floating-point instructions and Floating-Point Control instructions. Note that all Floating-Point Unit instruction mnemonics begin with an F. 12.2 Instruction Encoding 12.2.1 Overview All instruction encodings are subsets of the general instruction format shown in Figure 128.
Intel® Quark Core—Instruction Set Summary Table 75.
Instruction Set Summary—Intel® Quark Core 12.2.3 Encoding of Integer Instruction Fields Within the instruction are several fields that indicate register selection, addressing mode and so on. The exact encodings of these fields are defined in this section. 12.2.3.1 Encoding of Operand Length (w) Field For any given instruction that performs a data operation, the instruction executes as a 32-bit operation or a 16-bit operation.
Intel® Quark Core—Instruction Set Summary Table 78. Encoding of reg Field when the (w) Field is Present in Instruction Register Specified by reg Field during 16-Bit Data Operations: Function of w Field reg 000 (when w = 0) (when w = 1) AL AX 001 CL CX 010 DL DX 011 BL BX 100 AH SP 101 CH BP 110 DH SI 111 BH DI Register Specified by reg Field during 32-Bit Data Operations Function of w Field reg (when w = 0) 12.2.3.
Instruction Set Summary—Intel® Quark Core Table 80. 12.2.3.4 3-Bit sreg3 Field 3-bit sreg3 Field Segment Register Selected 000 ES 001 CS 010 SS 011 DS 100 FS 101 GS 110 do not use 111 do not use Encoding of Address Mode Except for special instructions, such as PUSH or POP, where the addressing mode is pre-determined, the addressing mode for the current instruction is specified by addressing bytes following the primary opcode.
Intel® Quark Core—Instruction Set Summary Table 81.
Instruction Set Summary—Intel® Quark Core Table 82.
Intel® Quark Core—Instruction Set Summary Table 83.
Instruction Set Summary—Intel® Quark Core 12.2.3.6 Encoding of Sign-Extend (s) Field The s field occurs primarily to instructions with immediate data fields. The s field has an effect only when the size of the immediate data is 8 bits and is being placed in a 16-bit or 32-bit destination. Table 85. Encoding of Sign-Extend (s) Field s 12.2.3.
Intel® Quark Core—Instruction Set Summary Table 87. Encoding of Control or Debug or Test Register (eee) Field eee Code TTReg Name When Interpreted as Control Register Field: 000 CR0 010 CR2 011 CR3 When Interpreted as Debug Register Field: 000 DR0 001 DR1 010 DR2 011 DR3 110 DR6 111 DR7 When Interpreted as Test Register Field: Note: 12.2.
Instruction Set Summary—Intel® Quark Core Table 88.
Intel® Quark Core—Instruction Set Summary In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that CMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. 12.2.5.2 RDMSR Description Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.
Instruction Set Summary—Intel® Quark Core This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to bits in a reserved MSR.
Intel® Quark Core—Instruction Set Summary When the destination instruction is not completely contained in the first 16 byte burst, add a maximum of r+3b bus clocks. 7. If no write buffer delay occurs, w bus clocks are added only when all write buffers are full. 8. Displacement and immediate must not be used together. If displacement and immediate are used together, one core clock may be added to the core clock count shown. 9. No invalidate cycles.
Instruction Set Summary—Intel® Quark Core Table 89.
Intel® Quark Core—Instruction Set Summary Table 89.
Instruction Set Summary—Intel® Quark Core Table 89. Clock Count Summary (Sheet 3 of 13) Instruction Format Cache Hit Penalty if Cache Miss Notes TEST = Logical Compare reg1 and reg2 1000 010w : 11 reg1 reg2 1 memory and register 1000 010w : mod reg r/m 2 immediate and register 1111 011w : 11 000 reg : immediate data 1 immediate and acc. 1010100w : immediate data 1 immediate and memory 1111 011w : mod 000 r/m : immediate data 2 2 2 MUL = Multiply (unsigned) acc.
Intel® Quark Core—Instruction Set Summary Table 89. Clock Count Summary (Sheet 4 of 13) Instruction Format Cache Hit Penalty if Cache Miss Notes IMUL = Integer Multiply (signed) acc. with register 1111 011w : 11 101 reg Multiplier-Byte Word Dword acc. with memory 5/5 5/6 6/12 MN/MX,3 MN/MX,3 MN/MX,3 5/5 5/6 6/12 MN/MX,3 MN/MX,3 MN/MX,3 5/5 5/6 6/12 MN/MX,3 MN/MX,3 MN/MX,3 5/5 5/6 6/12 MN/MX,3 MN/MX,3 MN/MX,3 0110 10s1 : 11 reg1 reg2 : immediate data Multiplier-Byte Word Dword mem.
Instruction Set Summary—Intel® Quark Core Table 89.
Intel® Quark Core—Instruction Set Summary Table 89. Clock Count Summary (Sheet 6 of 13) Instruction Format Cache Hit Penalty if Cache Miss Notes CONTROL TRANSFER (within segment) Note: Times are jump taken/not taken JCCCC = Jump on cccc 8-bit displacementt 0111 tttn : 8-bit disp.
Instruction Set Summary—Intel® Quark Core Table 89. Clock Count Summary (Sheet 7 of 13) Cache Hit Penalty if Cache Miss 1100 0011 5 5 1100 0010 : 16-bit disp. 5 5 Instruction Format Notes RET = Return from CALL (within segment) Adding Immediate to SP ENTER = Enter Procedure 1100 1000 : 16-bit disp., 8-bit level Level = 0 Level = 1 Level (L) > 1 LEAVE = Leave Procedure 14 17 17+3L 1100 1001 5 8 1 MULTIPLE-SEGMENT INSTRUCTIONS MOV = Move reg. to segment reg.
Intel® Quark Core—Instruction Set Summary Table 89. Clock Count Summary (Sheet 8 of 13) Instruction Format Cache Hit Penalty if Cache Miss Notes 13 8 R,7 17 35 9 12 P,9 P,9 14 8 R,7 18 36 9 12 P,9 P,9 17 2 R,7,22 19 32 42+TS 43+TS 3 6 3 3 P,9 P,9 P,10,9 P,10,9, 13 9 R,7,9 18 31 41+TS 42+TS 10 13 10 10 P,9 P,9 P,10,9 P,10,9, RET = Return from CALL intersegment 1100 1010 to same level to outet lever intersegment adding imm. to SP 1100 1010 : 16-bit disp.
Instruction Set Summary—Intel® Quark Core Table 89.
Intel® Quark Core—Instruction Set Summary Table 89.
Instruction Set Summary—Intel® Quark Core Table 89.
Intel® Quark Core—Instruction Set Summary Table 89.
Instruction Set Summary—Intel® Quark Core Table 89. Clock Count Summary (Sheet 13 of 13) Instruction Penalty if Cache Miss Cache Hit Format Notes RSM = Exit System Management Mode 0000 1111 : 1010 1010 SMBASE Relocation Auto HALT Restart I/O Trap Restart 452 456 465 External Interrupt INT+11 NMI = Non-Maskable Interrupt Page Fault VM86 Exceptions CLK STI INTn PUSHF POPF IRET IN Fixed Port Variable Port OUT Fixed Port Variable Port INS OUTS REP INS REPOUTS Note: Table 90.
Intel® Quark Core—Instruction Set Summary Table 91. Interrupt Clock Counts (Sheet 2 of 2) Value for INT Method Cache Hit Miss Penalty Notes Protected Mode Interrupt/Trap gate, same level Interrupt/Trap gate, different level Task Gate 44 71 37 + TS 6 17 3 9 9 9, 10 Virtual Mode Interrupt/Trap gate, different level Task Gate 82 37 + TS 17 3 10 Note: Table 92. See Table 92 for definitions and notes for items in this table.
Instruction Set Summary—Intel® Quark Core Table 92. Notes and Abbreviations (for Table 89 through Table 91) (Sheet 2 of 2) 1. 2. 3. 4. Assuming that the operand address and stack address fall in different cache sets. Always locked, no cache hit case. Clocks= 10 + max(log2(|m|),n) Clocks = {quotient(count/operand length)}*7+9 = 8 if count ≤ operand length (8/16/32) 5. Clocks = {quotient(count/operand length)}*7+9 = 9 if count ≤ operand length (8/16/32) 6.
Intel® Quark Core—Instruction Set Summary Table 93.
Instruction Set Summary—Intel® Quark Core Table 94. Floating-Point Clock Count Summary (Sheet 1 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) Notes DATA TRANSFER FLD = Real Load to ST(0) 32-bit memory 11011 001 : mod 000 r/m : s-i-b/disp. 3 2 64-bit memory 11011 101 : mod 000 r/m : s-i-b/disp. 3 3 80-bit memory 11011 011 : mod 101 r/m : s-i-b/disp.
Intel® Quark Core—Instruction Set Summary Table 94. Floating-Point Clock Count Summary (Sheet 2 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) Notes FXCH = Exchange ST(0) and ST(i) 11011 001 : 11001 ST(i) 4 COMPARISON INSTRUCTIONS FCOM = Compare ST(0) with Real 32-bit memory 11011 000 : mod 010 r/m : s-i-b/disp. 4 2 1 64-bit memory 11011 100 : mod 010 r/m : s-i-b/disp.
Instruction Set Summary—Intel® Quark Core Table 94. Floating-Point Clock Count Summary (Sheet 3 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) Notes CONSTANTS FLDZ = Load +0.0 Into ST(0) 11011 001 : 1110 1110 : 4 FLD1 = Load +1.
Intel® Quark Core—Instruction Set Summary Table 94. Floating-Point Clock Count Summary (Sheet 4 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) 10(8-20) 2 7(5-17) 10(8-20) 3 7(5-17) Notes FSUB = Subtract Real from ST(0) ST(0)←ST(0) – 32-bit memory 11011 000 : mod 100 r/m : s-i-b/disp. ST(0)←ST(0) – 64-bit memory 11011 100 : mod 100 r/m : s-i-b/disp.
Instruction Set Summary—Intel® Quark Core Table 94. Floating-Point Clock Count Summary (Sheet 5 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) Notes 73 2 70 3 73 3 70 3 73 70 3 73 70 3 FDIV = Divide ST(0) by Real ST(0)←ST(0)/ 32-bit memory 11011 000 : mod 110 r/m : s-i-b/disp. ST(0)←ST(0)/ 64-bit memory 11011 100 : mod 110 r/m : s-i-b/disp.
Intel® Quark Core—Instruction Set Summary Table 94. Floating-Point Clock Count Summary (Sheet 6 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) 24(20-35) 2 7(5-17) 22.5(19-32) 2 7(5-17) 25(23-27) 2 8 23.5(19-32) 2 8 87(85-89) 2 70 3 85.5(84-86) 2 70 3 87(85-89) 2 70 3 85.
Instruction Set Summary—Intel® Quark Core Table 94. Floating-Point Clock Count Summary (Sheet 7 of 8) Instruction Format Cache Hit Avg (Lower Range...
Intel® Quark Core—Instruction Set Summary Table 94. Floating-Point Clock Count Summary (Sheet 8 of 8) Instruction Format Cache Hit Avg (Lower Range... Upper Range) Penalty if Cache Miss Concurrent Execution Avg (Lower Range- Upper Range) Notes FCLEX = Clear exceptions 11011 011 : 1110 0010 7 4 67 67 56 56 4 4 4 4 FSTENV = Store environment 11011 011 : mod 110 r/m : s-i-b/disp.
Signal Descriptions—Intel® Quark Core Appendix A Signal Descriptions For pin diagrams and pin locations, refer to the individual processor datasheets. Table 95. Symbol CLK Intel® Quark SoC X1000 Core Pin Descriptions (Sheet 1 of 5) Type I Name and Function Clock provides the fundamental timing and the internal operating frequency for the Intel® Quark Core. All external timing parameters are specified with respect to the rising edge of CLK.
Intel® Quark Core—Signal Descriptions Table 95. Symbol LOCK# PLOCK# Intel® Quark SoC X1000 Core Pin Descriptions (Sheet 2 of 5) Type Name and Function O The Bus Lock pin indicates that the current bus cycle is locked. The Intel® Quark Core does not allow a bus hold when LOCK# is asserted (but address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle.
Signal Descriptions—Intel® Quark Core Table 95. Symbol Intel® Quark SoC X1000 Core Pin Descriptions (Sheet 3 of 5) Type Name and Function I The Soft Reset pin duplicates all the functionality of the RESET pin with the following two exceptions: 1. The SMBASE register retains its previous value. 2. When UP# (I) is asserted, SRESET does not have an effect on the host processor. For soft resets, SRESET should remain active for at least 15 CLK periods. SRESET is active high.
Intel® Quark Core—Signal Descriptions Table 95. Symbol FLUSH# Intel® Quark SoC X1000 Core Pin Descriptions (Sheet 4 of 5) Type I Name and Function Intel® The Cache Flush input forces the Quark Core to flush its entire internal cache. FLUSH# is active low and need only be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for recognition in any specific clock.
Signal Descriptions—Intel® Quark Core Table 95. Symbol Intel® Quark SoC X1000 Core Pin Descriptions (Sheet 5 of 5) Type Name and Function WRITE-BACK ENHANCED Intel® Quark Core SIGNAL PINS CACHE# O The CACHE# output indicates internal cacheability on read cycles and burst write-back on write cycles. CACHE# is asserted for cacheable reads, cacheable code fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles, special cycles, and write-through cycles.
Intel® Quark Core—Testability Appendix B Testability This appendix contains the following subsections: • Section B.1, “On-Chip Cache Testing” on page 296 • Section B.2, “Translation Lookaside Buffer (TLB) Testing” on page 300 • Section B.3, “Intel® Quark SoC X1000 Core JTAG” on page 304 B.1 On-Chip Cache Testing The on-chip cache testability hooks are designed to be accessible for assembly language testing of the cache. The Intel® Quark SoC X1000 Core contains a cache fill buffer and a cache read buffer.
Testability—Intel® Quark Core Cache Data Test Register: TR3 The cache fill buffer and the cache read buffer can only be accessed through TR3. Data to be written to the cache fill buffer must first be written to TR3. Data read from the cache read buffer must be loaded into TR3. TR3 is 32 bits wide while the cache fill and read buffers are 128 bits wide. 32 bits of data must be written to TR3 four times to fill the cache fill buffer.
Intel® Quark Core—Testability to TR3 initiates the write to the cache fill buffer. The cache fill buffer is loaded with 128 bits of data by writing to TR5 and TR3 four times using a different entry select location each time. Table 96.
Testability—Intel® Quark Core will be corrupted. This is because the testability operations use hardware that is used in normal memory accesses for the Intel® Quark SoC X1000 Core whether the cache is enabled or not. B.1.4 Flush Cache The control bits in TR5 must be written with 11 to flush the cache. None of the other bits in TR5 have any meaning when 11 is written to the control bits. Flushing the cache resets the LRU bits and the valid bits to 0, but does not change the cache tag or data arrays.
Intel® Quark Core—Testability Figure 130. TR4 Definition for Standard and Enhanced Bus Modes for the Write-Back Enhanced Intel® Quark SoC X1000 Core 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 TAG r V LRU TAG r r LRU 6 5 4 3 2 VALID (SET) r 1 0 r Standard Bus Mode TR4 V V H L Enhanced Bus Mode TR4 Figure 131.
Testability—Intel® Quark Core Figure 132. TLB Organization B.2.2 TLB Test Registers TR6 and TR7 The two TLB test registers are shown in Figure 133. TR6 is the command test register and TR7 is the data test register. External access to these registers is provided through MOV reg,TREG and MOV TREG,reg instructions. B.2.2.1 Command Test Register: TR6 TR6 contains the tag information and control information used in a TLB test.
Intel® Quark Core—Testability Figure 133. TLB Test Registers 31 12 11 10 9 V Linear Address 31 D D# 12 11 10 9 PCD PWT L2 Physical Address 8 7 6 5 4 2 1 Unused U 8 3 7 6 5 4 L1 L0 Unused Replacement Pointer Select (Writes) Hit Indication (Lookup) 3 2 0 Option 1 TR6 TLB Command Test Register 0 Unused TR7 TLB Data Test Register Replacement Pointer (Writes) Hit Location (Lookup) The seven TLB tag protection bits are described below.
Testability—Intel® Quark Core B.2.2.2 Data Test Register: TR7 TR7 contains the information stored or read from the data block during a TLB test operation. Before a TLB test write, TR7 contains the physical address and the page attribute bits to be stored in the entry. After a TLB test lookup hit, TR7 contains the physical address, page attributes, LRU bits and entry location from the access.
Intel® Quark Core—Testability TR6 must be written to initiate the TLB write operation. Bit 0 in TR6 must be reset to zero to indicate a TLB write. The 20-bit linear address and the seven page protection bits must also be written in TR6 to specify the tag portion of the TLB entry. Note that the three least significant bits of the linear address specify which of the eight sets in the data block is loaded with the physical address data. Thus only 17 of the linear address bits are stored in the tag array. B.
Testability—Intel® Quark Core Figure 134. TAP Controller State Diagram B.3.1.1 Test-Logic-Reset State In this state, the test logic is disabled so that normal operation of the device can continue unhindered. This is achieved by initializing the instruction register such that the IDCODE instruction is loaded. No matter what the original state of the controller, the controller enters Test-Logic-Reset state when the TMS input is held high (1) for at least five rising edges of TCK.
Intel® Quark Core—Testability B.3.1.4 Capture-DR State In this state, the JTAG register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The other test data registers, which do not have parallel input, are not changed. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low. B.3.1.
Testability—Intel® Quark Core B.3.1.9 Update-DR State The JTAG register is provided with a latched parallel output to prevent changes at the parallel output while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the JTAG register is selected, data is latched onto the parallel output of this register from the shift-register path on the falling edge of TCK.
Intel® Quark Core—Testability The test data register selected by the current instruction retains its previous value during this state. The instruction does not change in this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state. B.3.1.15 Exit2-IR State This is a temporary state.
Feature Determination—Intel® Quark Core Appendix C Feature Determination C.1 CPUID Instruction CPUID instruction returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers. The instruction's output values are dependent on the contents of the EAX register upon execution. Table 102 summarizes the information returned depending on the initial value loaded into EAX register.
Intel® Quark Core—Feature Determination Table 102. CPUID with PAE/XD/SMEP features implemented (Sheet 2 of 2) EAX value Register Return value 0x800000020x80000007 EAX,EBX, ECX,EDX 0x0 0x80000008 EAX 0x2020 EBX,ECX,EDX 0x0 † Information provided about the processor Bit 7-0: physical address width Bit 15-8: linear address bits When the value of Limit CPUID Maxval (bit 22 of IA32_MISC_ENABLE) is set to 1, all basic leaves above 3 should be invisible. In this case, leaf 7 returns all zeros.
Feature Determination—Intel® Quark Core Refer to the Intel application note, Intel Processor Identification with the CPUID Instruction, for more details: http://www.intel.com/content/www/us/en/processors/processor-identification-cpuidinstruction-note.html link C.2 Intel® Quark SoC X1000 Stepping The Intel® Quark SoC X1000 stepping is identified by both: • Processor ‘Family/Model/Stepping’ returned by the CPUID instruction. This will always return 0x590 for Intel® Quark SoC X1000.
