Specifications
Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
10 Order Number: 329679-001US
10.3.11.2Shutdown Indication Cycle .......................................................221
10.3.11.3Stop Grant Indication Cycle ......................................................221
10.3.12Bus Cycle Restart .................................................................................222
10.3.13Bus States...........................................................................................224
10.3.14Floating-Point Error Handling for the Intel
®
Quark SoC X1000 Core.............225
10.3.14.1Floating-Point Exceptions .........................................................225
10.3.15Intel
®
Quark SoC X1000 Core Floating-Point Error Handling in
AT-Compatible Systems.........................................................................226
10.4 Enhanced Bus Mode Operation for the Write-Back Enhanced Intel
®
Quark SoC X1000
Core ..............................................................................................................226
10.4.1 Summary of Bus Differences ..................................................................226
10.4.2 Burst Cycles.........................................................................................227
10.4.2.1 Non-Cacheable Burst Operation.................................................227
10.4.2.2 Burst Cycle Signal Protocol .......................................................228
10.4.3 Cache Consistency Cycles ......................................................................228
10.4.3.1 Snoop Collision with a Current Cache Line Operation....................229
10.4.3.2 Snoop under AHOLD................................................................230
10.4.3.3 Snoop During Replacement Write-Back ......................................234
10.4.3.4 Snoop under BOFF# ................................................................235
10.4.3.5 Snoop under HOLD..................................................................237
10.4.3.6 Snoop under HOLD during Replacement Write-Back.....................239
10.4.4 Locked Cycles ......................................................................................239
10.4.4.1 Snoop/Lock Collision................................................................241
10.4.5 Flush Operation....................................................................................241
10.4.6 Pseudo Locked Cycles............................................................................242
10.4.6.1 Snoop under AHOLD during Pseudo-Locked Cycles.......................242
10.4.6.2 Snoop under HOLD during Pseudo-Locked Cycles.........................243
10.4.6.3 Snoop under BOFF# Overlaying a Pseudo-Locked Cycle................244
11.0 Debugging Support...................................................................................................246
11.1 Breakpoint Instruction......................................................................................246
11.2 Single-Step Trap..............................................................................................246
11.3 Debug Registers..............................................................................................246
11.3.1 Linear Address Breakpoint Registers (DR[3:0]).........................................247
11.3.2 Debug Control Register (DR7) ................................................................247
11.3.3 Debug Status Register (DR6) .................................................................250
11.3.4 Use of Resume Flag (RF) in Flag Register.................................................251
12.0 Instruction Set Summary...........................................................................................252
12.1 Instruction Set ................................................................................................252
12.1.1 Floating-Point Instructions .....................................................................253
12.2 Instruction Encoding ........................................................................................253
12.2.1 Overview.............................................................................................253
12.2.2 32-Bit Extensions of the Instruction Set...................................................254
12.2.3 Encoding of Integer Instruction Fields......................................................255
12.2.3.1 Encoding of Operand Length (w) Field........................................255
12.2.3.2 Encoding of the General Register (reg) Field ...............................255
12.2.3.3 Encoding of the Segment Register (sreg) Field ............................256
12.2.3.4 Encoding of Address Mode........................................................257
12.2.3.5 Encoding of Operation Direction (d) Field....................................260
12.2.3.6 Encoding of Sign-Extend (s) Field..............................................261
12.2.3.7 Encoding of Conditional Test (tttn) Field .....................................261
12.2.3.8 Encoding of Control or Debug or Test Register (eee) Field.............261
12.2.4 Encoding of Floating-Point Instruction Fields.............................................262
12.2.5 Intel
®
Quark SoC X1000 Core Instructions...............................................263
12.2.5.1 CMPXCHG8B - Compare and Exchange Bytes ..............................263
12.2.5.2 RDMSR ..................................................................................264