Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
104 Order Number: 329679-001US
Reading a new entry into the TLB (TLB refresh) is a two step process handled by the
Intel
®
Quark SoC X1000 Core hardware. The sequence of data cycles to perform a TLB
refresh is as follows:
1. Read the correct page directory entry, as pointed to by the page base register and
the upper 10 bits of the linear address. The page base register is in Control
Register 3.
Optionally, perform a locked read/write to set the accessed bit in the directory
entry. The directory entry is read twice if the Intel
®
Quark SoC X1000 Core needs
to set any of the bits in the entry. If the page directory entry changes between the
first and second reads, the data returned for the second read is used.
2. Read the correct entry in the Page Table and place the entry in the TLB.
Optionally, perform a locked read/write to set the accessed and/or dirty bit in the
page table entry. Again, note that the page table entry actually is read twice if the
Intel
®
Quark SoC X1000 Core needs to set any of the bits in the entry. Like the
directory entry, if the data changes between the first and second read, the data
returned for the second read is used.
Note: The directory entry must always be read into the Intel
®
Quark SoC X1000 Core,
because directory entries are never placed in the paging TLB. Page faults can be
signaled from either the page directory read or the page table read. Page directory and
page table entries can be placed in the Intel
®
Quark SoC X1000 Core on-chip cache like
normal data.
6.4.9 Page-Fault Exceptions
Accesses using linear addresses may cause page-fault exceptions (#PF; exception 14).
An access to a linear address may cause page-fault exception for either of two reasons:
(1) there is no valid translation for the linear address; or (2) there is a valid translation
for the linear address, but its access rights do not permit the access.
As noted in Section 6.4.3.2, there is no valid translation for a linear address if the
translation process for that address would use a paging structure entry in which the P
flag (bit 0) is 0 or one that sets a reserved bit. If there is a valid translation for a linear
address, its access rights are determined as specified in Section 6.4.5.
Figure 45. Translation Lookaside Buffer