Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 105
Protected Mode Architecture—Intel
®
Quark Core
Figure 46 illustrates the error code that the processor provides on delivery of a page-
fault exception.
The following items explain how the bits in the error code describe the nature of the
page-fault exception:
• P flag (bit 0).
This flag is 0 if there is no valid translation for the linear address because the P flag
was 0 in one of the paging-structure entries used to translate that address.
• W/R (bit 1).
If the access causing the page-fault exception was a write, this flag is 1; otherwise,
it is 0. This flag describes the access causing the page-fault exception, not the
access rights specified by paging.
• U/S (bit 2).
If a user-mode access caused the page-fault exception, this flag is 1; it is 0 if a
supervisor-mode access did so. This flag describes the access causing the pagefault
exception, not the access rights specified by paging. User-mode and supervisor-
mode accesses are defined in Section 6.4.5.
• RSVD flag (bit 3).
This flag is 1 if there is no valid translation for the linear address because a
reserved bit was set in one of the paging-structure entries used to translate that
address. (Because reserved bits are not checked in a paging-structure entry whose
P flag is 0, bit 3 of the error code can be set only if bit 0 is also set.)
Bits reserved in the paging-structure entries are reserved for future functionality.
Software developers should be aware that such bits may be used in the future and
that a paging-structure entry that causes a page-fault exception on one processor
might not do so in the future.
Figure 46. Page-Fault Error Code