Specifications

Intel
®
Quark Core—Protected Mode Architecture
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
106 Order Number: 329679-001US
• I/D flag (bit 4).
This flag is 1 if (1) the access causing the page-fault exception was an instruction
fetch; and (2) either (a) CR4.SMEP = 1; or (b) both (i) CR4.PAE = 1 (either PAE
paging or IA-32e paging is in use); and (ii) IA32_EFER.NXE = 1. Otherwise, the
flag is 0. This flag describes the access causing the page-fault exception, not the
access rights specified by paging.
Page-fault exceptions occur only due to an attempt to use a linear address. Failures to
load the PDPTE registers with PAE paging (see Section 6.4.3.1) cause general
protection exceptions (#GP(0)) and not page-fault exceptions.
6.4.10 Paging Operation
The paging hardware operates in the following fashion. The paging unit hardware
receives a 32-bit linear address from the segmentation unit. The upper 20 linear
address bits are compared with all 32 entries in the TLB to determine if there is a
match. If there is a match (i.e., a TLB hit), then the 32-bit physical address is
calculated and is placed on the address bus.
If the page table entry is not in the TLB, the Intel
®
Quark SoC X1000 Core reads the
appropriate page directory entry. When P = 1 on the page directory entry, indicating
that the page table is in memory, then the Intel
®
Quark SoC X1000 Core reads the
appropriate page table entry and sets the Access bit. When P = 1 on the page table
entry, indicating that the page is in memory, the Intel
®
Quark SoC X1000 Core updates
the Access and Dirty bits as needed and fetches the operand. The upper 20 bits of the
linear address, read from the page table, are stored in the TLB for future accesses.
However, if P = 0 for either the page directory entry or the page table entry, the Intel
®
Quark SoC X1000 Core generates a page fault, exception 14.
The Intel
®
Quark SoC X1000 Core also generates an exception 14 page fault if the
memory reference violated the page protection attributes such as U/S or R/W (for
example, when trying to write to a read-only page). CR2 holds the linear address that
caused the page fault. If a second page fault occurs while the Intel
®
Quark SoC X1000
Core is attempting to enter the service routine for the first, the Intel
®
Quark SoC
X1000 Core invokes the page fault handler a second time, rather than the double fault
(exception 8) handler. Because exception 14 is classified as a fault, CS: EIP points to
the instruction causing the page fault. The 16-bit error code pushed as part of the page
fault handler contains status bits that indicate the cause of the page fault.
The 16-bit error code is used by the operating system to determine how to handle the
page fault. The upper portion of Figure 47 shows the format of the page-fault error
code and the interpretation of the bits.