Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 11
Contents—Intel
®
Quark Core
12.2.5.3 RDTSC .................................................................................. 264
12.2.5.4 WRMSR ................................................................................. 264
12.3 Clock Count Summary ..................................................................................... 265
12.3.1 Instruction Clock Count Assumptions ...................................................... 265
A Signal Descriptions ................................................................................................... 291
B Testability ............................................................................................................... 296
B.1 On-Chip Cache Testing..................................................................................... 296
B.1.1 Cache Testing Registers TR3, TR4 and TR5 .............................................. 296
B.1.2 Cache Testability Write ......................................................................... 297
B.1.3 Cache Testability Read.......................................................................... 298
B.1.4 Flush Cache......................................................................................... 299
B.1.5 Additional Cache Testing Features for Write-Back Enhanced Intel
®
Quark
SoC X1000 Core................................................................................... 299
B.2 Translation Lookaside Buffer (TLB) Testing ......................................................... 300
B.2.1 Translation Lookaside Buffer Organization................................................ 300
B.2.2 TLB Test Registers TR6 and TR7............................................................. 301
B.2.2.1 Command Test Register: TR6................................................... 301
B.2.2.2 Data Test Register: TR7........................................................... 303
B.2.3 TLB Write Test..................................................................................... 303
B.2.4 TLB Lookup Test .................................................................................. 304
B.3 Intel
®
Quark SoC X1000 Core JTAG................................................................... 304
B.3.1 Test Access Port (TAP) Controller ........................................................... 304
B.3.1.1 Test-Logic-Reset State ............................................................ 305
B.3.1.2 Run-Test/Idle State................................................................. 305
B.3.1.3 Select-DR-Scan State.............................................................. 305
B.3.1.4 Capture-DR State ................................................................... 306
B.3.1.5 Shift-DR State........................................................................ 306
B.3.1.6 Exit1-DR State ....................................................................... 306
B.3.1.7 Pause-DR State ...................................................................... 306
B.3.1.8 Exit2-DR State ....................................................................... 306
B.3.1.9 Update-DR State .................................................................... 307
B.3.1.10 Select-IR-Scan State............................................................... 307
B.3.1.11 Capture-IR State .................................................................... 307
B.3.1.12 Shift-IR State......................................................................... 307
B.3.1.13 Exit1-IR State ........................................................................ 307
B.3.1.14 Pause-IR State....................................................................... 307
B.3.1.15 Exit2-IR State ........................................................................ 308
B.3.1.16 Update-IR State ..................................................................... 308
B.3.2 TAP Controller Initialization.................................................................... 308
C Feature Determination .............................................................................................. 309
C.1 CPUID Instruction ........................................................................................... 309
C.2 Intel
®
Quark SoC X1000 Stepping..................................................................... 311
Figures
1Intel
®
Quark SoC X1000 Core used in Intel
®
Quark SoC X1000 .....................................21
2 Address Translation..................................................................................................24
3 Addressing Mode Calculations....................................................................................27
4 Data Types .............................................................................................................29
5 Data Types .............................................................................................................31
6 String and ASCII Data Types .....................................................................................32
7 Pointer Data Types...................................................................................................32
8 Big vs. Little Endian Memory Format...........................................................................33