Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 115
On-Chip Cache—Intel
®
Quark Core
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core supports two modes of
operation with respect to internal cache configurations: Standard Bus Mode (write-
through cache) and Enhanced Bus Mode (write-back cache). See Section 7.1.1 and
other write-back enhanced sections below for write-back cache information.
7.1.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core implements a unified cache,
with a total cache size of 16 Kbytes. The processor's on-chip cache supports a modified
MESI (modified / exclusive / shared / invalid) write-back cache consistency protocol.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core internal cache is configurable
as write-back or write-through on a line-by-line basis, provided the cache is enabled for
write-back operation. The cache is enabled for write-back operation by driving the
WB/WT# pin to a high state for at least two clocks before and two clocks after the
falling edge of RESET. Cache write-back and invalidations can be initiated by hardware
or software. Protocols for cache consistency and line replacement are implemented in
hardware to ease system design.
Once the cache configuration is selected, the Write-Back Enhanced Intel
®
Quark SoC
X1000 Core continues to operate in the selected configuration and can be changed to a
different configuration only by starting the RESET process again. Asserting SRESET
does not change the operating mode of the processor. WB/WT# has an internal pull
down; when WB/WT# is unconnected, the processor is in Standard Bus Mode, i.e., the
on-chip cache is write-through. Table 35 lists the two modes of operation and the
differences between the two modes.
Unless specifically noted, the following sections apply to the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core in Standard Bus Mode (write-through cache).
Table 35. Write-Back Enhanced Intel
®
Quark SoC X1000 Core WB/WT# Initialization
State of
WB/WT# at
Falling Edge of
RESET
Effect on Intel
®
Quark SoC X1000 Core Operation
WB/WT# = LOW
Processor is in Standard Bus Mode (write-through cache)
1. When FLUSH# is asserted, the internal cache is invalidated in one system CLK.
2. No Special FLUSH# acknowledge cycles appear on the bus after the assertion of
FLUSH#.
3. All write-back specific inputs are ignored (INV, WB/WT#).
4. SRESET does not clear the SMBASE register. It behaves much like a RESET
(invalidating the on-chip cache and resetting the CR0 register, for example). SRESET is
not an interrupt.
WB/WT# =
HIGH
Processor is in Enhanced Bus Mode (Write-Back Cache)
1. Write backs are performed when a cache flush is requested (via the FLUSH# pin or
the WBINVD instruction). The system must watch for the FLUSH# special cycles to
determine the end of the flush.
2. The special FLUSH# acknowledge cycles appear on the bus after the assertion of
the FLUSH# and after all the cache write backs (if any) are completed on the bus.
3. WB/WT# is sampled on a line-by-line basis to determine the state of a line to be
allocated in the cache (as a write through (S state) or as write back (E state)).
4. The WB/WT# and INV inputs are no longer ignored. HITM# and CACHE# are
driven during appropriate bus cycles.
5. PLOCK# is always driven inactive.
6. SRESET is an interrupt. SRESET does not reset the SMBASE register or flush the
on-chip cache. The CR0 register gets the same values as after RESET, with the
exception of the CD and NW bits. These two bits retain their previous status. See
Section 9.2.17.4, “Soft Reset (SRESET)” on page 163 and Table 41 for details on
SRESET for enhanced bus (write-back) mode.