Specifications

Intel
®
Quark Core—Contents
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
12 Order Number: 329679-001US
9 Base Architecture Registers .......................................................................................40
10 Flag Registers..........................................................................................................41
11 Intel
®
Quark SoC X1000 Core Segment Registers and Associated Descriptor Cache
Registers.................................................................................................................45
12 System-Level Registers.............................................................................................46
13 Control Registers .....................................................................................................47
14 Intel
®
Quark SoC X1000 Core CR4 Register .................................................................52
15 Floating-Point Registers.............................................................................................53
16 Floating-Point Tag Word ............................................................................................54
17 Floating-Point Status Word ........................................................................................55
18 Protected Mode FPU Instructions and Data Pointer Image in Memory (32-Bit Format) ........59
19 Real Mode FPU Instruction and Data Pointer Image in Memory (32-Bit Format).................59
20 Protected Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format)..........60
21 Real Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format).................60
22 FPU Control Word.....................................................................................................61
23 Real Address Mode Addressing ...................................................................................66
24 Protected Mode Addressing........................................................................................69
25 Paging and Segmentation..........................................................................................69
26 Descriptor Table Registers .........................................................................................71
27 Interrupt Descriptor Table Register Use.......................................................................72
28 Segment Descriptors.................................................................................................73
29 System Segment Descriptors .....................................................................................75
30 Gate Descriptor Formats............................................................................................76
31 Example Descriptor Selection.....................................................................................78
32 Segment Descriptor Caches for Real Address Mode (Segment Limit and Attributes Are
Fixed).....................................................................................................................79
33 Segment Descriptor Caches for Protected Mode (Loaded per Descriptor)..........................80
34 Segment Descriptor Caches for Virtual 8086 Mode within Protected Mode (Segment Limit
and Attributes are Fixed)...........................................................................................81
35 Four-Level Hierarchical Protection...............................................................................82
36 Intel
®
Quark Core TSS and TSS Registers....................................................................84
37 Sample I/O Permission Bit Map ..................................................................................85
38 Intel
®
Quark Core TSS .............................................................................................88
39 Simple Protected System...........................................................................................90
40 GDT Descriptors for Simple System.............................................................................91
41 Linear-Address Translation to a 4-KByte Page using PAE Paging......................................95
42 Linear-Address Translation to a 2-MByte Page using PAE Paging .....................................96
43 Formats of CR3 and Paging-Structure Entries in 32-bit Mode with PAE Paging Disabled ......98
44 Formats of CR3 and Paging-Structure Entries in 32-bit Mode with PAE Paging Enabled.......99
45 Translation Lookaside Buffer ....................................................................................104
46 Page-Fault Error Code.............................................................................................105
47 Page Fault System Information.................................................................................107
48 Virtual 8086 Environment Memory Management.........................................................108
49 Virtual 8086 Environment Interrupt and Call Handling .................................................111
50 On-Chip Cache Physical Organization ........................................................................114
51 On-Chip Cache Replacement Strategy .......................................................................119
52 Page Cacheability ...................................................................................................121
53 Basic SMI# Interrupt Service ...................................................................................128
54 Basic SMI# Hardware Interface................................................................................129
55 SMI# Timing for Servicing an I/O Trap......................................................................130
56 Intel
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Quark SoC X1000 Core SMIACT# Timing..........................................................130
57 Redirecting System Memory Addresses to SMRAM.......................................................132
58 Transition to and from System Management Mode ......................................................135
59 SMM Revision Identifier...........................................................................................138
60 Auto HALT Restart..................................................................................................139