Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
120 Order Number: 329679-001US
The state of the PCD bit in the page table entry is driven on the PCD pin when a page in
external memory is accessed. The state of the PCD pin informs the external system of
the cacheability of the requested information. The external system then returns KEN#,
telling the Intel
®
Quark SoC X1000 Core whether the area is cacheable. The Intel
®
Quark SoC X1000 Core initiates a cache line fill when PCD and KEN# indicate that the
requested information is cacheable.
The PCD bit is OR’ed with the CD (cache disable) bit in control register 0 to determine
the state of the PCD pin. When CD=1, the Intel
®
Quark SoC X1000 Core forces the PCD
pin HIGH. When CD=0, the PCD pin is driven with the value for the page table
entry/directory (see Figure 52).
The PWT and PCD bits for a bus cycle are obtained from CR3, the page directory or
page table entry. These bits are assumed to be zero during Real Mode, whenever
paging is disabled, or for cycles that bypass paging (I/O references, interrupt
acknowledge cycles, and HALT cycles).
When paging is enabled, the bits from the page table entry are cached in the TLB, and
are driven when the page mapped by the TLB entry is referenced. For normal memory
cycles, PWT and PCD are taken from the page table entry. During TLB refresh cycles in
which the page table and directory entries are read, the PWT and PCD bits must be
obtained elsewhere. During page table updates the bits are obtained from the page
directory. When the page directory is updated, these bits are obtained from CR3. PCD
and PWT bits are initialized to zero at reset, but can be modified by level 0 software.