Specifications

Intel

Quark SoC X1000 Core

October 2013 Developer’s Manual

Order Number: 329679-001US 121

On-Chip Cache—Intel

Quark Core

Figure 52. Page Cacheability

7.6.1 Write-Back Enhanced Intel

Quark SoC X1000 Core and

Processor Page Cacheability

In Write-Back Enhanced Intel

Quark SoC X1000 Core-based systems, both the

processor and the system hardware must determine the cacheability and the

configuration (write-back or write-through) on a line-by-line basis. The system

hardware's cacheability is determined by KEN# and the configuration by WB/WT#. The

processor's indication of cacheability is determined by PCD and the configuration by

PWT. The PWT bit controls the write policy for the second-level caches used with the

Write-Back Enhanced Intel

Quark SoC X1000 Core. Setting PWT to 1 defines a write-

through policy for the current page, while clearing PWT to 0 defines a write-back policy

for the current page.

Cache Control Logic

Cache Memory

CR0