Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
122 Order Number: 329679-001US
7.7 Cache Flushing
The on-chip cache can be flushed by external hardware or by software instructions.
Flushing the cache clears all valid bits for all lines in the cache. The cache is flushed
when external hardware asserts the FLUSH# pin.
The FLUSH# pin must to be asserted for one clock when driven synchronously or for
two clocks when driven asynchronously. FLUSH# is asynchronous, but setup and hold
times must be met for recognition in a particular cycle. FLUSH# should be deasserted
before the cache flush is complete. Failure to deassert the pin causes execution to stop
as the processor repeatedly flushes the cache. When external hardware activates
FLUSH# in response to an I/O write, FLUSH# must be asserted for at least two clocks
prior to ready being returned for the I/O write. This ensures that the flush completes
before the processor begins execution of the instruction following the OUT instruction.
The instructions INVD and WBINVD cause the on-chip cache to be flushed. External
caches connected to the Intel
®
Quark SoC X1000 Core are signaled to flush their
contents when these instructions are executed.
WBINVD also cause an external write-back cache to write back dirty lines before
flushing its contents. The external cache is signaled using the bus cycle definition pins
and the byte enables. Refer to Section 9.2.5, “Bus Cycle Definition” on page 152 for the
bus cycle definition pins and Section 10.3.11, “Special Bus Cycles” on page 220 for
special bus cycles.
The results of the INVD and WBINVD instructions are identical for the operation of the
non-write-back enhanced Intel
®
Quark SoC X1000 Core on-chip cache because the
cache is write-through.
7.7.1 Write-Back Enhanced Intel
®
Quark SoC X1000 Core Cache
Flushing
The on-chip cache can be flushed by external hardware or by software instructions.
Flushing the cache through hardware is accomplished by asserting the FLUSH# pin.
This causes the cache to write back all modified lines in the cache and mark the state
bits invalid. The first flush acknowledge cycle is driven by the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core, followed by the second flush acknowledge cycle after all
write-backs and invalidations are complete. The two special cycles are issued even
when there are no dirty lines to write back.
The INVD and WBINVD instructions cause the on-chip cache to be invalidated. WBINVD
causes the modified lines in the internal cache to be written back, and all lines to be
marked invalid. After execution of the WBINVD instruction, the write-back and flush
special cycles are driven to indicate to external cache that it should write back and
invalidate its contents. These two special cycles are issued even when there are no
dirty lines to be written back. INVD causes all lines in the cache to be invalidated, so
modified lines in the cache are not written back. The Flush special cycle is driven after
the INVD instruction is executed to indicate to any external cache that it should
invalidate its contents. Care should be taken when using the INVD instruction to avoid
creating cache consistency problems.
Note: It is recommended to use the WBINVD instruction instead of the INVD instruction when
the on-chip cache is configured in write-back mode.
The assertion of RESET invalidates the entire cache without writing back the modified
lines. No special cycles are issued after the invalidation is complete.