Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
124 Order Number: 329679-001US
With the modified MESI protocol it is assumed that in a uniprocessor system, lines are
defined as write-back or write-through at allocation time. This property associated with
a line is never altered. The lines allocated as write-through go to S-state and remain in
S-state. A cache line that is allocated as write-back never enters the S-state. The
WB/WT# pin is sampled during line allocation and is used strictly to characterize a line
as write-back or write-through.
State Transition Tables
State transitions are caused by processor-generated transactions (memory
reads/writes) and by a set of external input signals and internally-generated variables.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core also drives certain pins as a
consequence of the cache consistency protocol.
Read Cycles
Table 39 shows the state transitions for lines in the cache during unlocked read cycles.
Write Cycles
The state transitions of cache lines during Write-Back Enhanced Intel
®
Quark SoC
X1000 Core-generated write cycles are described in Table 40.
Table 39. Cache State Transitions for Write-Back Enhanced Intel
®
Quark SoC X1000
Core-Initiated Unlocked Read Cycles
Present
State
Pin Activity Next State Description
Mn/aM
Read hit; data is provided to processor core by cache.
No bus cycle is generated.
En/aE
Read hit; data is provided to processor core by cache.
No bus cycle is generated.
Sn/aS
Read hit; Data is provided to the processor by the
cache. No bus cycle is generated.
I
CACHE# low
AND
KEN# low
AND
WB/WT# high
AND
PWT low
E Data item does not exist in cache (MISS).
I
CACHE# low
AND
KEN# low
AND
(WB/WT# low
OR PWT high)
S
Same as previous read miss case except that WB/WT#
is sampled low with first BRDY# or PWT is high.
I
CACHE# high
OR
KEN# high
I
KEN# pin inactive; the line is not intended to be
cached in the Write-Back Enhanced Intel
®
Quark SoC
X1000 Core.
Notes:
1. Locked accesses to the cache cause the accessed line to transition to the Invalid state.
2. PCD can also be used by the processor to determine the cacheability, but using the CACHE# pin is
recommended. The transition from I to E or S states (based on WB/WT#) occurs only when KEN# is
sampled low one clock prior to the first BRDY# and then one clock prior to the last BRDY#, and the
cycle is transformed into a line fill cycle. When KEN# is sampled high, the line is not cached and
remains in the I state.