Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 125
On-Chip Cache—Intel
®
Quark Core
Note that even though memory writes are buffered while I/O writes are not, these
writes appear at the pins in the same order as they were generated by the processor.
Write-back cycles caused by the replacement of M-state lines are buffered, while write
backs due to snoop hit to M-state lines are not buffered.
Cache Consistency Cycles (Snoop Cycles)
The purpose of snoop cycles is to check whether the address being presented by
another bus master is contained within the cache of the Write-Back Enhanced Intel
®
Quark SoC X1000 Core. Snoop cycles may be initiated with or without an invalidation
request (INV = 1 or 0). When a snoop cycle is initiated with INV = 0 (usually during
memory read cycles by another master), it is referred to as an inquire cycle. When a
snoop cycle is initiated with INV = 1 (usually during memory write cycles), it is referred
to as an invalidate cycle. When the address hits a modified line in the cache, HITM# is
asserted and the modified line is written back to the bus. Table 41 describes state
transitions for snoop cycles.
7.8.2 Detecting On-Chip Write-Back Cache of the Write-Back
Enhanced Intel
®
Quark SoC X1000 Core
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core write-back policy for the on-
chip cache can be detected by software or hardware. The software mechanism uses the
CPUID instruction. (See Section C.1, “CPUID Instruction” on page 309 for details.) The
hardware mechanism uses a write-back related output signal from the processor.
Table 40. Cache State Transitions for Write-Back Enhanced Intel
®
Quark SoC X1000
Core-Initiated Write Cycles
Present
State
Pin
Activity
Next
State
Description
M n/a M Write hit; update cache. No bus cycle generated to update memory.
En/aM
Write hit; update cache only. No bus cycle generated; line is now
modified.
Sn/aS
Write hit; cache updated with write data item. A write-through cycle
is generated on the bus to update memory. Subsequent writes to E-
state or M-state lines are held up until this write through cycle is
completed.
In/aI
Write miss; a write-through cycle is generated on the bus to update
external memory. No allocation is done. Subsequent writes to the E
or M lines are blocked until the write miss is completed.
Table 41. Cache State Transitions During Snoop Cycles
Present
State
Next
State
INV=1
Next
State
INV=0
Description
MI E
Snoop hit to a modified line indicated by HITM# low. The state of the
line changes to E provided INV = 0 and changes to I when INV = 1.
EI E
Snoop hit, no bus cycle generated. State remains unaltered when
INV = 0, and changes to I when INV = 1. There is no external
indication of this snoop hit.
SI S
Snoop hit, no bus cycle generated. State remains unaltered when
INV = 0, and changes to I when INV = 1. There is no external
indication of this snoop hit.
I I I Address not in cache.