Specifications

Intel
®
Quark Core—On-Chip Cache
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
126 Order Number: 329679-001US
A software mechanism to determine whether a processor has write-back support for
the on-chip cache should drive the WB/WT# pin to ‘1’ during RESET. This pin is sampled
by the processor during the falling edge of RESET. Execute the CPUID instruction, which
returns the model number in the EAX register, EAX[7:4]. When the model number
returned is 7 (identifying the presence of a Write-Back Enhanced Intel
®
Quark SoC
X1000 Core) and the family number is 4, the on-chip cache supports the write-back
policy. When the model number returned is in the range 0 through 6 or 8, the on-chip
cache supports the write-through policy only.
The following pseudo code/steps give an example of the initialization BIOS that can
detect the presence of the write-back on-chip cache:
• Boot address cold start
• Load segment registers and null IDTR
• Execute CPUID instruction and determine the family ID and model ID.
• Compare the family ID to 4 and the Model ID to the values listed in Table 103.
The hardware mechanism for detecting the presence of write-back cache uses the
HITM# signal. For the Write-Back Enhanced Intel
®
Quark SoC X1000 Core, this signal
is driven inactive (high) during RESET. The chipset can sample this output on the falling
edge of RESET. When HITM# is sampled high on the falling edge of RESET, the
processor supports on-chip write-back cache configuration. For those processors that
do not support internal write-back caching, this signal is an INC, and this output is not
driven.