Specifications

Intel
®
Quark Core—System Management Mode (SMM) Architectures
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
128 Order Number: 329679-001US
SMBASE Control register that contains the address of the SMRAM space.
Context The processor state just before the processor invokes SMM. The
context normally consists of the processor registers that fully
represent the processor state.
Context Switch The process of either saving or restoring the context. The SMM
discussion refers to the context switch as the process of
saving/restoring the context while invoking/exiting SMM,
respectively.
8.3 System Management Interrupt Processing
The system interrupts the normal program execution and invokes SMM by generating a
System Management Interrupt (SMI#) to the processor. The processor services the
SMI# by executing the following sequence (see Figure 53):
1. The processor asserts SMIACT#, indicating to the system that it should enable the
SMRAM.
2. The processor saves its state (context) to SMRAM, starting at default address
location 3FFFFH, proceeding downward in a stack-like fashion.
3. The processor switches to the System Management Mode processor environment (a
pseudo-real mode).
Figure 53. Basic SMI# Interrupt Service
4. The processor then jumps to the default absolute address of 38000H in SMRAM to
execute the SMI# handler. This SMI# handler performs the system management
activities.
5. The SMI# handler then executes the RSM instruction (which restores the
processors context from SMRAM), de-asserts the SMIACT# signal, and then returns
control to the previously interrupted program execution.
Note: The above sequence is valid for the default SMBASE value only. See the following
sections for a description of the SMBASE register and SMBASE relocation.
A5237-01
State Resume
SMI#
SMM HandlerState Slave
InstrInstr Instr
#3#1 #2
InstrInstr
#5#4
Cache must
be empty
Cache must
be empty
Flush cache
SMIACT#
SMI#
RSM